13.22.3 Packet Timing

While no data are being transmitted, a logic ‘1’ must be placed on the open-drain DE2 line by the host dsPIC DSC using an internal pull-up resistor. A data packet is composed of one Start bit, which is always a logic ‘0’, followed by eight data bits and a Stop bit. The Stop bit must always be a logic ‘1’. It takes 10 bits to transmit a byte of data.

The DE2 interface detects the Start bit by detecting the transition from logic ‘1’ to logic ‘0’ (note that while the data line is Idle, the logic level is high). Once the Start bit is detected, the next data bit’s center can be assured to be 24 ticks minus 2 (worst-case synchronizer uncertainty) later. From then on, every next data bit center is 16 clock ticks later. Figure 13-6 illustrates basic packet timing.