13.20.1 External Drive for A 3-Phase Bridge with NMOS/NMOS MOSFET Pairs

Each motor phase is driven with external NMOS/NMOS MOSFET pairs. These are controlled by a low-side and a high- side gate driver. The gate drivers are controlled by the host dsPIC PWM interconnects. A logic high turns the associated gate driver on, and a logic low turns the associated gate driver off.

The low-side gate drivers are biased by the V_BOOT regulator output, referenced to ground. The high-side gate drivers are a floating drive biased by a bootstrap capacitor circuit. The bootstrap capacitor is charged by the V_BOOT regulator whenever the accompanying low-side MOSFET is turned on.

The high-side and low-side driver outputs all go to a Low state whenever there is a Fault, when OE = 0 for more than 1 ms or when Sleep mode is active, regardless of the PWM[A:C]H/L inputs.