26.6.1 Control A
Name: | CTRLA |
Offset: | 0x00 |
Reset: | 0x0000 |
Property: | PAC Write-Protection |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CMDEX[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CMD[6:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 15:8 – CMDEX[7:0] Command Execution
When this bit group is written to the key value 0xA5, the command written to CMD will be executed. If a value different from the key value is tried, the write will not be performed and the Programming Error bit in the Status register (STATUS.PROGE) will be set. PROGE is also set if a previously written command is not completed yet.
The key value must be written at the same time as CMD. If a command is issued through the APB bus on the same cycle as an AHB bus access, the AHB bus access will be given priority. The command will then be executed when the NVM block and the AHB bus are idle.
INTFLAG.READY must be '1' when the command is issued.
Bit 0 of the CMDEX bit group will read back as '1' until the command is issued.
Bits 6:0 – CMD[6:0] Command
These bits define the command to be executed when the CMDEX key is written.
CMD[6:0] | Group Configuration | Description |
---|---|---|
0x00-0x01 | - | Reserved |
0x02 | ER | Erase Row - Erases the row addressed by the ADDR register in the NVM main array. |
0x03 | - | Reserved |
0x04 | WP | Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. |
0x05 | EAR |
Erase Configuration Rows- Erases the Configuration Rows addressed by the ADDR register. This command can be given only when the Security bit (DSU STATUSB.PROT or NVMCTRL STATUS.SB) is not set and only to the User Configuration Row. |
0x06 | WAP |
Write Configuration Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the Security bit (DSU STATUSB.PROT or NVMCTRL STATUS.SB) is not set and only to the User Configuration Row. |
0x07-0x19 | - | Reserved |
0x1A | DFER | Data Flash Erase Row - Erases the row addressed by the ADDR register in the Data Flash. |
0x1B | - | Reserved |
0x1C | DFWP | Data Flash Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register in the Data Flash. |
0x1D-0x3F | - | Reserved |
0x40 | LR | Lock Region - Locks the region containing the address location in the ADDR register. |
0x41 | UR | Unlock Region - Unlocks the region containing the address location in the ADDR register. |
0x42 | SPRM | Sets the Power Reduction mode. |
0x43 | CPRM | Clears the Power Reduction mode. |
0x44 | PBC | Page Buffer Clear - Clears the page buffer. |
0x45 | SSB | Set Security Bit - Sets the Security bit. The protection only becomes effective after the next chip reset. The Security Bit status will be visible in DSU STATUSB.PROT or NVMCTRL STATUSB.SB) |
0x46 | INVALL | Invalidates all cache lines. |
0x47-0x7E | - | Reserved |
0x7F | SCEHL | Set Chip Erase Hard Lock. Sets the CEHL bit and permanently disables
the Chip-Erase feature. This command can only be issued by software once
the Security Bit has been set with the SSB command and the device has
been reset. Once set, it is not possible to erase it anymore. CAUTION: Microchip's failure analysis capabilities are limited when this
feature is used. |