26.6.12 ECC Control
| Name: | ECCCTRL |
| Offset: | 0x80 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SECCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ECCDFDIS | ECCDIS | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bits 15:8 – SECCNT[7:0] Flash SEC Count
SECCNT is the start value of an internal counter that decrements (by 1) its count value each time an SEC event occurs. The internal counter stops decrementing at zero. If an SEC error occurs when the internal counter is zero, the INTFLAG.SERR flag bit is set. The set value is not automatically reloaded when the counter reaches 0.
Bit 1 – ECCDFDIS Data Flash section ECC Disable
Writing '0' will have no effect.
Writing '1' will disable the ECC for the Data Flash.
Once disabled, it cannot be re-enabled manually, and will only be re-enabled automatically after the next reset.
| Value | Description |
|---|---|
| 0 | Data Flash ECC is enabled |
| 1 | Data Flash ECC is disabled |
Bit 0 – ECCDIS Flash Main array ECC Disable
Writing '0' will have no effect.
Writing '1' will disable the ECC for the main array.
Once disabled, it cannot be re-enabled manually, and will only be re-enabled automatically after the next reset.
| Value | Description |
|---|---|
| 0 | Flash main array ECC is enabled |
| 1 | Flash main array ECC is disabled |