26.6.6 Interrupt Flag Status and Clear
| Name: | INTFLAG |
| Offset: | 0x14 |
| Reset: | 0x00 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FLTCAP | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLASHERR | DERR | SERR | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | READY | ||||||||
| Access | R/W | R | |||||||
| Reset | 0 | 0 |
Bit 24 – FLTCAP Fault Capture
This flag is cleared by writing a '1' to the flag.
This flag is set when a Fault Capture has occurred and will generate an interrupt request if INTENSET.FLTCAP = 1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the FLTCAP interrupt flag.
Bit 11 – FLASHERR FLASHERR Double Error Detection
This flag is set when a double error is detected at startup during hardware read of the flash user row, and will generate an interrupt request if INTENSET.FLASHERR = 1.
This interrupt is always enabled and can only be set by hardware upon read of the user row, and only be cleared by a reset. This bit will be ORed with the DERR.
Writing a '0' or a '1' to this bit has no effect.
Bit 9 – DERR Double Bit Error Detection
This flag is cleared by writing a '1' to the flag.
This flag is set when an ECC double bit error is detected, and will generate an interrupt request if INTENSET.DERR = 1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the DERR interrupt flag.
Bit 8 – SERR Single Bit Error Detection
This flag is cleared by writing a '1' to the flag.
This flag is set when an ECC single or double bit error is detected, and will generate an interrupt request if INTENSET.SERR = 1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the SERR interrupt flag.
Bit 1 – ERROR Error
This flag is cleared by writing a '1' to the flag.
This flag is set on the occurrence of an NVME, LOCKE, or PROGE error, and will generate an interrupt request if INTENSET.ERROR = 1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the ERROR interrupt flag.
Bit 0 – READY NVM Ready
| Value | Description |
|---|---|
| 0 | The NVM controller is busy programming or erasing. |
| 1 | The NVM controller is ready to accept a new command. |
