26.6.4 Interrupt Enable Clear
Name: | INTENCLR |
Offset: | 0x0C |
Reset: | 0x00 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
FLTCAP | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
DERR | SERR | ||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ERROR | READY | ||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit 24 – FLTCAP Fault Capture Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the FLTCAP Interrupt Enable bit, which disables the FLTCAP interrupt.
Value | Description |
---|---|
0 | The FLTCAP interrupt is disabled. |
1 | The FLTCAP interrupt is enabled. |
Bit 9 – DERR Double Bit Error Detection Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the DERR Interrupt Enable bit, which disables the DERR interrupt.
Value | Description |
---|---|
0 | The DERR interrupt is disabled. |
1 | The DERR interrupt is enabled. |
Bit 8 – SERR Single Bit Error Detection Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the SERR Interrupt Enable bit, which disables the SERR interrupt.
Value | Description |
---|---|
0 | The SERR interrupt is disabled. |
1 | The SERR interrupt is enabled. |
Bit 1 – ERROR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the ERROR Interrupt Enable bit, which disables the ERROR interrupt.
Value | Description |
---|---|
0 | The ERROR interrupt is disabled. |
1 | The ERROR interrupt is enabled. |
Bit 0 – READY NVM Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the READY Interrupt Enable bit, which disables the READY interrupt.
Value | Description |
---|---|
0 | The READY interrupt is disabled. |
1 | The READY interrupt is enabled. |