26.6.4 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x0C
Reset: 0x00
Property: PAC Write-Protection

Bit 3130292827262524 
        FLTCAP 
Access R/W 
Reset 0 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
       DERRSERR 
Access R/WR/W 
Reset 00 
Bit 76543210 
       ERRORREADY 
Access R/WR/W 
Reset 00 

Bit 24 – FLTCAP Fault Capture Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the FLTCAP Interrupt Enable bit, which disables the FLTCAP interrupt.

ValueDescription
0 The FLTCAP interrupt is disabled.
1 The FLTCAP interrupt is enabled.

Bit 9 – DERR Double Bit Error Detection Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the DERR Interrupt Enable bit, which disables the DERR interrupt.

Note: This bit is only available on PIC32CM5164 and PIC32CM2532 variants.
ValueDescription
0 The DERR interrupt is disabled.
1 The DERR interrupt is enabled.

Bit 8 – SERR Single Bit Error Detection Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the SERR Interrupt Enable bit, which disables the SERR interrupt.

Note: This bit is only available on PIC32CM5164 and PIC32CM2532 variants.
ValueDescription
0 The SERR interrupt is disabled.
1 The SERR interrupt is enabled.

Bit 1 – ERROR Error Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the ERROR Interrupt Enable bit, which disables the ERROR interrupt.

ValueDescription
0 The ERROR interrupt is disabled.
1 The ERROR interrupt is enabled.

Bit 0 – READY NVM Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the READY Interrupt Enable bit, which disables the READY interrupt.

ValueDescription
0 The READY interrupt is disabled.
1 The READY interrupt is enabled.