26.6.8 Address

Name:	ADDR
Offset:	0x1C
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
			ADDR[21:16]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ADDR[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ADDR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 21:0 – ADDR[21:0] NVM Address

ADDR drives the hardware half-word offset address to the NVM when a command is executed using CMDEX. This register is also automatically updated when writing to the page buffer.

Example:

For erasing the 3rd row in the Flash memory, spanning from 0x00000200 to 0x000002FF, ADDR should be written with the half-word offset address of any half-word within this range, that is any value between 0x100 and 0x17F.

For erasing the 5th row in the Data Flash memory, spanning from 0x00400400 to 0x004004FF, ADDR should be written with the half-word offset address of any half-word within this range, that is any value between 0x200 and 0x27F.