26.6.19 Debug Control Register

Note: This Register is only available on PIC32CM5164 and PIC32CM2532 variants.
Name: DBGCTRL
Offset: 0x9C
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      DBGECC[1:0]  
Access R/WR/W 
Reset 00 

Bits 2:1 – DBGECC[1:0] Debug ECC Mode

Value Description
0x0 ECC errors from debugger reads are corrected, No Bus error is generated, INTFLAG is not updated and FLT logic is not updated. (except ECCCTRL.SECCNT which is decremented upon each SEC error)
0x1 ECC errors from debugger reads are not corrected, No Bus Error is generated, INTFLAG is not updated, and FLT logic is not updated. (except ECCCTRL.SECCNT which is decremented upon each SEC error)
0x2 ECC errors from debugger reads are corrected, Bus Error is generated when conditions are met, INTFLAG is updated and FLT logic operates as setup.
0x3 ECC errors from debugger reads are not corrected, No Bus Error is generated, INTFLAG is not updated, and FLT logic is not updated. (except ECCCTRL.SECCNT which is decremented upon each SEC error)