5.15.11.9 Device Status Register 2
| Name: | DSR2 |
| Offset: | 0x11 |
| Reset: | 0x0 |
| Property: | R |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Reserved | VDD2OVS | VDD1OVS | VDD2UVS | VDD1UVHS | VDD1UVLS | VGUVS | VCPUVS | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – Reserved
(Submit Feedback)Reserved, do not modify reset value!
Bit 6 – VDD2OVS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | VDD2 overvoltage is detected. |
| 0 | VDD2 voltage is below the overvoltage clear level. |
Bit 5 – VDD1OVS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | VDD1 overvoltage is detected. |
| 0 | VDD1 voltage is below the overvoltage clear level. |
Bit 4 – VDD2UVS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | VDD2 undervoltage is detected. |
| 0 | VDD2 voltage is above the undervoltage clear level. |
Bit 3 – VDD1UVHS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | VDD1 undervoltage is detected. |
| 0 | VDD1 voltage is above the undervoltage clear level (VVDD1 > VVDD1_UV_CLR). |
Bit 2 – VDD1UVLS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | VDD1 IO undervoltage is detected, |
| 0 | VDD1 voltage is above the undervoltage clear level (VVDD1 > VVDD1_IO_UV_CLR), |
Bit 1 – VGUVS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | VG undervoltage is detected. |
| 0 | VG voltage level is higher than the VVGS_UV_Clear_H threshold. |
Bit 0 – VCPUVS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | VCP undervoltage is detected. |
| 0 | VCP voltage level is higher than the VVGS_UV_Clear_H threshold. |