11.5.26 Transmit Matched Packet Delay Register

Name: TXMDLY
Address: 0x0049

Bit 15141312111098 
 TXMDLYENTXMPKTDLY[10:8] 
Access R/WRORORORORORORO 
Reset 00000000 
Bit 76543210 
 TXMPKTDLY[7:0] 
Access RORORORORORORORO 
Reset 00000000 

Bit 15 – TXMDLYEN Transmit Matched Packet Delay Measurement Enable

When set, this bit enables the measurement of matched transmit packet delays through the PHY.
ValueDescription
0 Transmit packet delay measurement is disabled
1 Transmit packet delay measurement is enabled

Bits 10:0 – TXMPKTDLY[10:0] Transmit Matched Packet Delay

This field contains the delay of the previously matched transmit packet through the PHY. The delay is measured from the assertion of TXEN to the end of the transmission of the first SSD symbol (’H”) of the packet preamble onto the line units of 40 ns. When PLCA is enabled, the measured delay includes the delay of the packet through the PLCA elastic buffer.
ValueDescription
0x000 0 ns
0x001 40 ns
... ...
0x7FF 81.880 μs