11.5.33 Receive Matched Packet Delay Register

Name: RXMDLY
Address: 0x0059

Bit 15141312111098 
 RXMDLYENRXMPKTDLY[10:8] 
Access R/WRORORORORORORO 
Reset 00000000 
Bit 76543210 
 RXMPKTDLY[7:0] 
Access RORORORORORORORO 
Reset 00000000 

Bit 15 – RXMDLYEN Receive Matched Packet Delay Measurement Enable

When set, this bit enables the measurement of matched receive packet delays through the PHY.
ValueDescription
0 Receive packet delay measurement is disabled
1 Receive packet delay measurement is enabled

Bits 10:0 – RXMPKTDLY[10:0] Receive Matched Packet Delay

This field contains the delay of the previously matched receive packet through the PHY. The delay is measured from detection of the first SSD symbol (’H”) of the packet preamble on the line to the assertion of Receive Data Valid at the media interface. The delay in this field is represented in units of 10 ns with an uncertainly of 10 ns.
ValueDescription
0x000 0 ns
0x001 10 ns
0x010 20 ns
... ...
0x7FF 20.470 μs