11.5.4 Status 3 Register
| Name: | STS3 |
| Address: | 0x001A |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | RO | RO | RO | RO | RO | RO | RO | RO | |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERRTOID[7:0] | |||||||||
| Access | RO | RO | RO | RO | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – ERRTOID[7:0] PLCA Error Transmit Opportunity ID
Note: This
field is only accurate if one unmasked interrupt status bit is set in the Status 1
register. If multiple interrupt status bits are set, then this field represents the
transmit opportunity for only the most recent interrupt status
bit.
