Description
Conformity
1 Preface
2 Introduction
3 Pin Descriptions and Assignments
4 Global Functional Descriptions
5 Serial Peripheral Interface (SPI)
6 Ethernet MAC
7 Integrated PHY
8 Application Information
9 Operational Characteristics
10 Packaging Information
11 Register Descriptions
- 11.1 Open Alliance 10BASE-T1x MAC-PHY Standard Registers
- 11.2 MAC Registers
- 11.3 PHY PCS Registers
- 11.4 PHY PMA/PMD Registers
- 11.5 PHY Vendor Specific Registers
  - 11.5.1 Control 1 Register
    Control 1 Register
  - 11.5.2 Status 1 Register
    Status 1 Register
  - 11.5.3 Status 2 Register
    Status 2 Register
  - 11.5.4 Status 3 Register
    Status 3 Register
  - 11.5.5 Interrupt Mask 1 Register
    Interrupt Mask 1 Register
  - 11.5.6 Interrupt Mask 2 Register
    Interrupt Mask 2 Register
  - 11.5.7 Counter Control Register
    Counter Control Register
  - 11.5.8 Transmit Opportunity Count (High)
    Transmit Opportunity Count (High)
  - 11.5.9 Transmit Opportunity Count (Low)
    Transmit Opportunity Count (Low)
  - 11.5.10 BEACON Count (High)
    BEACON Count (High)
  - 11.5.11 BEACON Count (Low)
    BEACON Count (Low)
  - 11.5.12 PLCA Multiple ID 0 Register
    PLCA Multiple ID 0 Register
  - 11.5.13 PLCA Multiple ID 1 Register
    PLCA Multiple ID 1 Register
  - 11.5.14 PLCA Multiple ID 2 Register
    PLCA Multiple ID 2 Register
  - 11.5.15 PLCA Multiple ID 3 Register
    PLCA Multiple ID 3 Register
  - 11.5.16 PLCA Reconciliation Sublayer Status
    PLCA Reconciliation Sublayer Status
  - 11.5.17 Port Management 2
    Port Management 2
  - 11.5.18 Inactivity Watchdog Timeout (High)
    Inactivity Watchdog Timeout (High)
  - 11.5.19 Inactivity Watchdog Timeout (Low)
    Inactivity Watchdog Timeout (Low)
  - 11.5.20 Transmit Match Control Register
    Transmit Match Control Register
  - 11.5.21 Transmit Match Pattern (High) Register
    Transmit Match Pattern (High) Register
  - 11.5.22 Transmit Match Pattern (Low) Register
    Transmit Match Pattern (Low) Register
  - 11.5.23 Transmit Match Mask (High) Register
    Transmit Match Mask (High) Register
  - 11.5.24 Transmit Match Mask (Low) Register
    Transmit Match Mask (Low) Register
  - 11.5.25 Transmit Match Location Register
    Transmit Match Location Register
  - 11.5.26 Transmit Matched Packet Delay Register
    Transmit Matched Packet Delay Register
  - 11.5.27 Receive Match Control Register
    Receive Match Control Register
  - 11.5.28 Receive Match Pattern (High) Register
    Receive Match Pattern (High) Register
  - 11.5.29 Receive Match Pattern (Low) Register
    Receive Match Pattern (Low) Register
  - 11.5.30 Receive Match Mask (High) Register
    Receive Match Mask (High) Register
  - 11.5.31 Receive Match Mask (Low) Register
    Receive Match Mask (Low) Register
  - 11.5.32 Receive Match Location Register
    Receive Match Location Register
  - 11.5.33 Receive Matched Packet Delay Register
    Receive Matched Packet Delay Register
  - 11.5.34 Credit Based Shaper Stop Threshold (High) Register
    Credit Based Shaper Stop Threshold (High) Register
  - 11.5.35 Credit Based Shaper Stop Threshold (Low) Register
    Credit Based Shaper Stop Threshold (Low) Register
  - 11.5.36 Credit Based Shaper Start Threshold (High) Register
    Credit Based Shaper Start Threshold (High) Register
  - 11.5.37 Credit Based Shaper Start Threshold (Low) Register
    Credit Based Shaper Start Threshold (Low) Register
  - 11.5.38 Credit Based Shaper Slope Control Register
    Credit Based Shaper Slope Control Register
  - 11.5.39 Credit Based Shaper Top Limit (High) Register
    Credit Based Shaper Top Limit (High) Register
  - 11.5.40 Credit Based Shaper Top Limit (Low) Register
    Credit Based Shaper Top Limit (Low) Register
  - 11.5.41 Credit Based Shaper Bottom Limit (High) Register
    Credit Based Shaper Bottom Limit (High) Register
  - 11.5.42 Credit Based Shaper Bottom Limit (Low) Register
    Credit Based Shaper Bottom Limit (Low) Register
  - 11.5.43 Credit Based Shaper Credit Counter (High) Register
    Credit Based Shaper Credit Counter (High) Register
  - 11.5.44 Credit Based Shaper Credit Counter (Low) Register
    Credit Based Shaper Credit Counter (Low) Register
  - 11.5.45 Credit Based Shaper Control Register
    Credit Based Shaper Control Register
  - 11.5.46 PLCA Skip Control Register
    PLCA Skip Control Register
  - 11.5.47 PLCA Transmit Opportunity Skip Register
    PLCA Transmit Opportunity Skip Register
  - 11.5.48 Application Controlled Media Access Control Register
    Application Controlled Media Access Control Register
  - 11.5.49 Sleep Control 0 Register
    Sleep Control 0 Register
  - 11.5.50 Sleep Control 1 Register
    Sleep Control 1 Register
  - 11.5.51 Collision Detector Control 0 Register
    Collision Detector Control 0 Register
  - 11.5.52 SQI Control Register
    SQI Control Register
  - 11.5.53 SQI Status 0 Register
    SQI Status 0 Register
  - 11.5.54 SQI Configuration 0 Register
    SQI Configuration 0 Register
  - 11.5.55 SQI Configuration 2 Register
    SQI Configuration 2 Register
  - 11.5.56 Analog Control 5
    Analog Control 5
  - 11.5.57 OPEN Alliance Map ID and Version Register
    OPEN Alliance Map ID and Version Register
  - 11.5.58 PLCA Control 0 Register
    PLCA Control 0 Register
  - 11.5.59 PLCA Control 1 Register
    PLCA Control 1 Register
  - 11.5.60 PLCA Status Register
    PLCA Status Register
  - 11.5.61 PLCA Transmit Opportunity Timer Register
    PLCA Transmit Opportunity Timer Register
  - 11.5.62 PLCA Burst Mode Register
    PLCA Burst Mode Register
- 11.6 Miscellaneous Register Descriptions
Data Sheet Revision History
Microchip Information

11.5.50 Sleep Control 1 Register

Name:	SLPCTL1
Address:	0x0081


Bit	15	14	13	12	11	10	9	8

Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	WOPOL		WIPOL			MWKFWD	WKOFWDEN	MDIFWDEN
Access	R/W	R/W	R/W	RO	R/W	R/W SC	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – WOPOL WAKE_OUT Polarity

This bit configures the polarity of the 90 μs output wake pulse generated on the WAKE_OUT pin.

Note: Only wake from HIGH pulses on WAKE_OUT is supported.

Restriction: While this bit defaults to ‘0’, it must always be written to ‘1’ when writing to other bits in this register.

Value	Description
`0`	Reserved
`1`	Device will output an active HIGH pulse on the WAKE_OUT pin.

Bit 5 – WIPOL WAKE_IN Polarity

This bit configures the polarity of the pulse on the WAKE_IN pin that will wake the device from sleep.

Value	Description
`0`	Device will wake from an active LOW pulse on WAKE_IN pin.
`1`	Device will wake from an active HIGH pulse on WAKE_IN pin.

Bit 2 – MWKFWD Manual Wake Forward

When set, this bit will trigger a wake forwarding event. The device will generate a wake-up pulse on WAKE_OUT if forwarding of wake events to WAKE_OUT is enabled by WAKE_OUT Forward Enable (WKOFWDEN) bit. Wake activity signaling will be generated to the MDI if forwarding of wake events to MDI is enabled by MDI Wake Forward Enable (MDIFWDEN) bit.

Note: This bit is self-cleared by hardware once the wake output events have completed.

Value	Description
`0`	No wake out signaling (normal operation)
`1`	Generate wake out signaling to WAKE_OUT and/or MDI

Bit 1 – WKOFWDEN WAKE_OUT Forward Enable

Enable the generation of a WAKE_OUT pulse when a wake indication is detected by MDI activity or assertion of the WAKE_IN pin.

Value	Description
`0`	Disable generation of a pulse on WAKE_OUT on wake-up
`1`	Enable generation of a pulse on WAKE_OUT on wake-up

Bit 0 – MDIFWDEN MDI Forward Enable

This bit will enable the generation of activity signaling on the MDI when a wake indication is detected by the assertion of the WAKE_IN pin.

Value	Description
`0`	Disable generation MDI wake signaling upon wake-up from WAKE_IN
`1`	Enable generation MDI wake signaling upon wake-up from WAKE_IN

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