38.7.13 Comparator Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CMPCTRL |
| Offset: | 0x0B0 |
| Reset: | 0x00000000 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| IEHIHI | IEHILO | ADCMPHI[11:8] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ADCMPHI[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| IEBTWN | IELOHI | IELOLO | CMPEN | ADCMPLO[11:8] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADCMPLO[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 29 – IEHIHI Enable VAL >= CMPHI
Setting this bit enables comparison events ADCMPHI≤ ADC value.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
- The Digital Comparator works on the final value of the filter data.
- When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefore in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
- In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRL.
Bit 28 – IEHILO Enable VAL < CMPHI
Setting this bit enables comparison events ADC value < ADCMPHI.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
- The Digital Comparator works on the final value of the filter data.
- When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
- In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRL.
Bits 27:16 – ADCMPHI[11:0] High Limit of Digital Comparator
This register stores the limit value which is used for comparisons with the ADC Module output data when
IEHIHI = 1, IEHILO = 1, or IEBTWN = 1.
The user is responsible for formatting the data in ADCMPHI[11:0] as signed or unsigned to match the data format as specified by the CHNCFG3.SIGNk and CHNCFG2.FRACTk bits for all the analog input channels k which are enabled by CHNCFG1.CHNCMPENk .
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
- The Digital Comparator works on the final value of the filter data.
- When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
- In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRL.
Bit 15 – IEBTWN Enable CMPLO <= VAL < CMPHI
Setting this bit enables comparison events ADCMPLO ≤ ADC Value < ADCMPHI.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
- The Digital Comparator works on the final value of the filter data.
- When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
- In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRL.
Bit 14 – IELOHI Enable VAL >= CMPLO
Setting this bit enables comparison events ADCMPLO≤ ADC Value.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
- The Digital Comparator works on the final value of the filter data.
- When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
- In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRL.
| Value | Description |
|---|---|
| 0 | Use normal interrupts |
| 1 | use early interrupts |
Bit 13 – IELOLO Enable VAL < CMPLO
Setting this bit enables comparison events ADC Value < ADCMPLO.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
- The Digital Comparator works on the final value of the filter data.
- When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
- In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRL.
Bit 12 – CMPEN Comparator Enable
Setting this bit enables digital comparisons for the inputs to the ADC.
For each channel input channel k to be compared the corresponding bit CHNCFG1.CHNCMPENk must be set for the channel to be monitored.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
- The Digital Comparator works on the final value of the filter data.
- When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
- In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRL.
Bits 11:0 – ADCMPLO[11:0] Low Limit of Digital Comparator
This register stores the limit value which is used for comparisons with the ADC Module output data when
IELOHI = 1, IELOLO = 1, or IEBTWN = 1.
The user is responsible for formatting the data in ADCMPLO[11:0] as signed or unsigned to match the data format as specified by the CHNCFG3.SIGNk and CHNCFG2.FRACTk bits for all the analog input channels k which are enabled by CHNCFG1.CHNCMPENk .
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
- The Digital Comparator works on the final value of the filter data.
- When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
- In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRL.