38.7.4 Control D Register

Table 38-11. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: CTRLD
Offset: 0x010
Reset: 0x00000000
Property: RW

Bit 3130292827262524 
  VREFSEL[2:0]WKUPEXP[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 2322212019181716 
 ANLEN3ANLEN2ANLEN1ANLEN0CHNEN3CHNEN2CHNEN1CHNEN0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
   CTLCKDIV[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
          
Access  
Reset  

Bits 30:28 – VREFSEL[2:0] Voltage Reference Select

VREFSEL[2:0]ADREF+ADREF-
000AVDDAVSS
001External VREFHAVSS
010-111ReservedReserved
Note:
  1. This bit is Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and return a bus error.
ValueNameDescription
0AVDD_AVSSAVDD and AVSS
1EXTERNAL_VREFH_AVSSExternal VREFH and AVSS

Bits 27:24 – WKUPEXP[3:0] Wakeup cycles

These bits represent the number of ADC TAD clocks required to warm-up the ADC module before it can perform conversion.

1111 = 215 = 32,768 TAD clocks

* * *

* * *

0110 = 26 = 64 TAD clocks

0101 = 25 = 32 TAD clocks

0100 = 24 = 16 TAD clocks

0011 = 24 = 16 TAD clocks

0010 = 24 = 16 TAD clocks

0001 = 24 = 16 TAD clocks

0000 = 24 = 16 TAD clocks

Note:
  1. Minimum required ADC warm-up time, (i.e., WKUPCLKCNT), is 50 μs. (i.e., TAD * WKUPCLKCNT).
  2. TAD = [1 / ((GCLK_ADC Freq / (CTRLD.CTLCKDIV+1)) / (2 * CORCTRL.ADCDIV)) ] or

    (GCLK_ADC Period * (CTRLD.CTLCKDIV+1)) * (2 * ADCDIV).

  3. These bits are Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and return a bus error.

Bit 23 – ANLEN3 Analog and Bias circuitry Enable for core 3

Bit 22 – ANLEN2 Analog and Bias circuitry Enable for core 2

Bit 21 – ANLEN1 Analog and Bias circuitry Enable for core 1

Bit 20 – ANLEN0 Analog and Bias circuitry Enable for core 0

Note:
  1. The CALCTRL register must be initialized by the users software to the factory-provided values in the Calibration Configuration Register FCCFG65 before setting ANLEN0=1.
  2. CTRLA.ANAEN=1 must be set prior to setting ANLEN0=1.
  3. This bit is Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and return a bus error.
ValueDescription
0ADC Analog and bias circuitry powered down and clocks suspended. Analog logic power saving mode.
1Analog and bias circuitry enabled. Once the analog and bias circuit is enabled CTRLA.ANLEN=1 and ANLEN, the ADC module needs a warm-up time, as defined by the WKUPEXP<3:0> bits.

Bit 19 – CHNEN3 Core 3 Digital Channel Enable

Bit 18 – CHNEN2 Core 2 Digital Channel Enable

Bit 17 – CHNEN1 Core 1 Digital Channel Enable

Bit 16 – CHNEN0 Core 0 Digital Channel Enable

Note:
  1. This bit is Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and return a bus error.
  2. ANLEN0 qualifies CHNEN0: If ANLEN0 =0, then digital logic is also disabled.
ValueDescription
0ADC digital logic disabled. No trigger, sample or conversion events will be processed. (power-saving mode with fast 2 TAD clock wakeup provided ANLEN0 = 1).
1ADC digital logic enabled (required for active operation).

Bits 13:8 – CTLCKDIV[5:0] Control Clock Divider

The CTLCKDIV bit field divides the GCLK_ADC input clock into the ADC Module control clock CTL_CLK scaled by CTRLD.CTLCKDIV with period TQ.

Note: This bit is Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and returns a bus error.
ValueDescription
111111TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 64·TGCLK_ADCx = TQ
111110TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 63·TGCLK_ADCx = TQ
......
000100TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 5·TGCLK_ADCx = TQ
000011TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 4·TGCLK_ADCx = TQ
000010TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 3·TGCLK_ADCx = TQ
000001TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 2·TGCLK_ADCx = TQ
000000TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 1·TGCLK_ADCx = TQ