38.7.19 DMA Control Register

Table 38-26. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	DMACTRL
Offset:	0x0E0
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
						DMABL[2:0]
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	7	6	5	4	3	2	1	0
	DMACR3	DMACR2	DMACR1	DMACR0			DMAEN
Access	R/W	R/W	R/W	R/W			R/W
Reset	0	0	0	0			0

Bits 10:8 – DMABL[2:0] DMA System RAM Buffer Length

Bit 7 – DMACR3 DMA CORE3 Enable

Bit 6 – DMACR2 DMA CORE2 Enable

Bit 5 – DMACR1 DMA CORE1 Enable

Bit 4 – DMACR0 DMA CORE0 Enable

Bit 1 – DMAEN DMA Enable

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