38.7.2 CONTROL B REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLB |
| Offset: | 0x004 |
| Reset: | 0x00000000 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SWCNVEN | STRGEN | TRGSUSP | LSWTRG | GSWTRG | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SAMP | RQCNVRT | ADCORSEL[1:0] | ADCHSEL[3:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – SWCNVEN Software Conversion Enable
Note: When CTRLB.SWCNVEN=1, the
channels sample and conversions are controlled exclusively by SAMP and RQCNVRT.
All hardware triggers and GSWTRG and LSWTRG are disabled. It will place the ADC
module and all of its channels under the exclusive control of the CTRLB.SAMP and
CTRLB.RQCNVRT bits.
| Value | Description |
|---|---|
| 0 | Software controlled conversions disable. Traditional ADC hardware triggers as defined by CHNCFG4 and CHNCFG5 will be active if enabled. |
| 1 | SAMP and RQCNVRT bits control entire ADC module sample and convert respectively for all channels. Setting this bit blocks all other hardware triggers events defined by CHNCFG4 and CHNCFG5. |
Bit 11 – STRGEN Synchronous Trigger Enable
Note: This bit is ignored if
CTRLB.SWCNVEN=1.
| Value | Description |
|---|---|
| 0 | Disable automatic ADC hardware CTRLC.CNT counter driven synchronous ADC triggers. |
| 1 | Enable automated hardware synchronous trigger period defined by CTRLC.CNT register. |
Bit 10 – TRGSUSP Trigger Suspend
| Value | Description |
|---|---|
| 0 | Trigger suspend disabled. Triggers if enabled and selected will occur. |
| 1 | Blocks triggers from starting new ADC conversions but does not disable the ADC Modules or disable trigger capture, (i.e. persistent last trigger event is latched). If trigger capture during trigger suspend is not desired for any channels, then CTRLD.CHNEN0 must be cleared then set in that order prior to resetting TRGSUSP. Pulsing down and up CTRLD.CHNEN0 prior to resetting TRGSUSP will clear ALL pending triggers. |
Bit 9 – LSWTRG Level Global Trigger
Note:
- This bit is ignored if SWCNVEN=1.
- If SWCNVEN=0, this bit is NOT self-clearing and is meant to allow the user software to implement continuous sample/conversions on the associated analog input channel.
| Value | Description |
|---|---|
| 0 | Global Level Software Trigger disabled. |
| 1 | Trigger A/D conversions for ADC analog input(s) "y" that have selected LSWTRG bit as the trigger signal via the associated CHNCFG4.TRGSRC[y] or CHNCFG5.TRGSRC[y] = 0b0010 or via the CORCTRL.STRGSRC. |
Bit 8 – GSWTRG Global Software Trigger
This software settable bit will trigger ADC sample/conversion sequences for ADC inputs that have selected the GSWTRG bit as the trigger signal via the associated CHNCFG4.TRGSRC[y] or CHNCFG5.TRGSRC[y], via the CORCTRL.STRGSRC value. This bit is auto cleared on the next APB clock cycle and is meant to implement single conversions on trigger edge-sensitive channels.
Note:
- This bit is ignored if SWCNVEN=1.
| Value | Description |
|---|---|
| 0 | Disable Global Software Trigger. |
| 1 | If SWCNVEN=0, this bit is auto cleared by hardware after sampling cycle has been triggered and is meant to implement single sample/conversions on trigger edge-sensitive channels. |
Bit 7 – SAMP Channel Sample
Note:
- This bit is ignored if SWCNVEN = 0.
- ADCHSEL[3:0] must be initialized at or before when the SAMP bit is set.
- The SAMP bit will keep the S&H circuit in Sample mode until the bit is cleared by the users software. Also, usage of the SAMP bit will cause settings of respective CORCTRL.SAMC<9:0> bits to be ignored.
- The SAMP bit is not a self-clearing bit and it is the responsibility of application software to clear this bit but only after setting the RQCNVRT bit to start the analog-to-digital conversion.
- When the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx<4:0> bits and STRGSRC<4:0> bits should be set to ‘00000’ to disable all hardware triggers and prevent them from interfering with the software-controlled sampling command signal SAMP and with the software controlled trigger RQCNVRT.
- The SAMP bit should only be used in conjunction with RQCNVRT for user software-controlled sampling and triggering.
| Value | Description |
|---|---|
| 0 | ADC is not software-controlled. Sampling the channel selected by ADCHSEL[3:0]. |
| 1 | ADC is sampling and remain sampling for as long as user has this bit set in SW. The sampled analog input is defined by ADCHSEL[3:0] provided SWCNVEN = 1. |
Bit 6 – RQCNVRT Request Channel Convert
Note:
- If user’s software sets RQCNVRT = 1, an ADC conversion will begin immediately and terminate the sampling period defined by CORCTRL.SAMC. This bit is cleared by hardware after the conversion is complete.
- If SWCNVEN = 1, after setting this bit the users software must immediately clear the SAMP bit.
- This bit is ignored if SWCNVEN = 0, (i.e. if software-controlled sample/conversions are disabled).
| Value | Description |
|---|---|
| 0 | ADC is not converting if SWCNVEN = 1 or user previously set this bit and the previous ADC conversion is complete for the analog channel that was defined by ADCHSEL[3:0] |
| 1 | Terminate sampling and begin conversion of ADC and analog channel defined by ADCHSEL[3:0]. This bit is cleared by hardware when the conversion is complete. |
Bits 5:4 – ADCORSEL[1:0] Software Trigger Core Select
Bits 3:0 – ADCHSEL[3:0] Software Trigger Channel Select
This binary encoded bit field selects the ADC analog input to be sampled and converted respectively by the SAMP and RQCNVRT bit if SWCNVEN = 1.
Note: These bits are ignored if SWCNVEN = 0.
| ADCHSEL[3:0] | Analog Channel Input |
|---|---|
| 0x0 | AIN0 |
| 0x1 | AIN1 |
| 0x2 | AIN2 |
| 0x3 | AIN3 |
| 0x4 | AIN4 |
| 0x5 | AIN5 |
| 0X6 | AIN6 |
| 0x7 | AIN7 |
| 0x8 | AIN8 |
| 0x9 | AIN9 |
| 0xA | AIN10 |
| 0xB | AIN11 |
| 0xC | VDDCORE_SW |
| 0xD | Reserved |
| 0xE | 1.2V IVREF |
| 0xF | Reserved |