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38.7.6 Channel Configuration 1 (LVL/CMPEN)
Table 38-13. Register Bit Attribute
Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: CHNCFG1 Offset: 0x024 Reset: 0x00000000 Property: RW
Bit 31 30 29 28 27 26 25 24 LVL[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16 LVL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 CHNCMPEN[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 CHNCMPEN[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 31:16 – LVL[15:0] Channel Level
Bits 15:0 – CHNCMPEN[15:0] Channel Comparator Enable
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