38.7.26 CORE Controller Interrupt Enable Clear

Note: Writing a zero to these bits has no effect. Writing a one to these any of these bits will CLEAR the ENABLE bit.
Note: A read of this register provides whether the Interrupt is Enabled (bit=1) or Disabled (bit=0), i.e. a write of a 1 to the bit then a read of the bit will return the interrupt is disabled (=0).
Table 38-33. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: CTLINTENCLR
Offset: 0x100
Reset: 0x00000000
Property: RW

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     PFFHFULPFFRDYPFFOVFPFFUNF 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 VREFRDYVREFUPD  CRRDY3CRRDY2CRRDY1CRRDY0 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 11 – PFFHFUL APB FIFO Half Full

Writing a 1 to this bit will disable the ADC FIFO Half Full as an interrupt request.

Reading this bit returns whether the PFFHFUL interrupt is enabled (1 = enabled).

Bit 10 – PFFRDY APB FIFO Ready

Writing a 1 to this bit will disable the ADC FIFO Data Ready as an interrupt request.

Reading this bit returns whether the PFFRDY interrupt is enabled (1 = enabled).

Bit 9 – PFFOVF APB FIFO overflow

Writing a 1 to this bit will disable the ADC FIFO Overflow Error as an interrupt request,

Reading this bit returns whether the PFFOVF interrupt is enabled (1 = enabled).

Bit 8 – PFFUNF APB FIFO underflow

Writing a 1 to this bit will disable the ADC FIFO Read Underflow Error as an interrupt request.

Reading this bit returns whether the PFFUNF interrupt is enabled (1 = enabled).

Bit 7 – VREFRDY VREF Ready

Writing a 1 to this bit will disable the ADC Voltage Reference Ready as an interrupt request.

Reading this bit returns whether the VREFRDY interrupt is enabled (1 = enabled).

Bit 6 – VREFUPD VREF Update

Writing a 1 to this bit will disable the ADC Voltage Reference Ready Updated as an interrupt request.

Reading this bit returns whether the VREFUPD interrupt is enabled (1 = enabled).

Bit 3 – CRRDY3 Core Ready 3 Disable

Bit 2 – CRRDY2 Core Ready 2 Disable

Bit 1 – CRRDY1 Core Ready 1 Disable

Bit 0 – CRRDY0 Core Ready 0 Disable

Writing a 1 to this bit will disable the Core n Ready as an interrupt request.

Reading this bit returns whether the CRRDY interrupt is enabled (1 = enabled).