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38.7.24 DMA Interrupt Flag and Status
Table 38-31. Register Bit Attribute
Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: DMAINTFLAG Offset: 0x0F8 Reset: 0x00000000 Property: RW
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 DMAERR SOVFL Access R/HS/K R/K Reset 0 0
Bit 15 14 13 12 11 10 9 8 EBF[3:0] EAF[3:0] Access R/HS/K R/HS/K R/HS/K R/HS/K R/HS/K R/HS/K R/HS/K R/HS/K Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 RBF[3:0] RAF[3:0] Access R/K R/K R/K R/K R/K R/K R/K R/K Reset 0 0 0 0 0 0 0 0
Bit 17 – DMAERR DMA Bus Error
Bit 16 – SOVFL Synchronizer overflow
Bits 15:12 – EBF[3:0] Ram Buffer B Overflow Error
Bits 11:8 – EAF[3:0] Ram Buffer A Overflow Error
Bits 7:4 – RBF[3:0] Ram Buffer B Full
Bits 3:0 – RAF[3:0] Ram Buffer A Full
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