38.7.30 Interrupt Flags
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTFLAG |
| Offset: | 0x128 |
| Reset: | 0x00000000 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CHRDY[15:8] | |||||||||
| Access | R/K | R/K | R/K | R/K | R/K | R/K | R/K | R/K | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CHRDY[7:0] | |||||||||
| Access | R/K | R/K | R/K | R/K | R/K | R/K | R/K | R/K | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CRDYID[3:0] | EOSRDY | CHNERRC | FLTRDY | CHRDYC | |||||
| Access | R/K | R/K | R/K | R/K | R/K | R/K | R/K | R/K | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SOVFL | CMPHIT | CMPINTID[3:0] | |||||||
| Access | R/K | R/K | R/K | R/K | R/K | R/K | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 31:16 – CHRDY[15:0] Channel Ready
CHRDY[ k ] = 1 indicates that ADC has completed its last A/D conversion for channel k.
CHRDY[ k ] is reset by software writing a 1 to it.
Bits 15:12 – CRDYID[3:0] Channel Ready ID
The value of CRDYID indicates the input channel index, k , that ADC has just completed in its current scan. This if for information only since these bits cannot be used to trigger an ADC interrupt. (CHRDY[ k ] are intended for that purpose.)
These bits are reset by software writing a 1 to them.
Bit 11 – EOSRDY End of Scan Ready
This bit is set by hardware at the end of the scan of all channels included in the scan performed by ADC in response to a SINGLE event of the Scan Trigger 0 (STRIG0).
If INTENSET.EOSRDY is set, then EOSRDY = 1 will trigger an ADC interrupt.
This bit is reset by software writing a 1 to it.
Bit 10 – CHNERRC Channel Overwrite Error
When set, this bit indicates that the ADC has completed its last A/D conversion for channel CRDYID[3:0], but at the time CRDYID[3:0] was updated, the status bit CHRDYC was still set, which indicates that the software may not have had the time to read the previous data, which may be now lost.
If INTENSET.CHNERRC is set, then CHNERRC = 1 will trigger an ADC interrupt.
This bit is reset by software writing a 1 to it.
Bit 9 – FLTRDY Filter Ready
When set, this bit indicates that the digital filter has issued a new output sample for the input channel defined by FLTCTRL.FLTCHNID.
If INTENSET.FLTRDY is set, then FLTRDY = 1 will trigger an ADC interrupt.
This bit is reset by software writing a 1 to it.
Bit 8 – CHRDYC Current Channel Ready
0 = ADC busy or idle.
1 = When set, this bit signifies that the ADC has completed its current A/D conversion for the channel identified in CRDYID[3:0].
- If INTENSET.CHRDYC is set, then CHRDYC = 1 will trigger an ADC interrupt.
- This bit is reset by software writing a 1 to it.
Bit 7 – SOVFL Synchronizer Overflow
When set this bit signifies the ADC data was lost due to a slow APB_CLK.
If INTENSET.SOVFL is set, then SOVFL = 1 will trigger an ADC interrupt.
This bit is reset by software writing a 1 to it.
Bit 4 – CMPHIT Compare Hit
When set, this bit signifies that the Digital Comparator associated with ADC has issued a condition hit interrupt for channel identified in CMPINTID[5:0].
If INTENSET.CMPHIT is set, then CMPHIT = 1 will trigger an ADC interrupt.
This bit is reset by software writing a 1 to it.
Bits 3:0 – CMPINTID[3:0] Compare Channel ID
When set, this signifies that the ADC Channel ID for which the digital comparator has issued the condition hit interrupt (CMPHIT=1). These bits cannot be used as an interrupt request flag. This is for information only. (CMPHIT is intended for that purpose.)
This bit is reset by software writing a 1 to it.