38.7.20 APB FIFO Control Register

The ADC FIFO is useful in applications that stream out ADC data at very high transfer rates to relive CPU bandwidth. Individual high data rate ADC result interrupts and CPU reads may slow bus access transfer requests.

Table 38-27. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: PFFCTRL
Offset: 0x0E4
Reset: 0x00000000
Property: RW

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
        PFFRDYDM 
Access R/W 
Reset 0 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 PFFCR3PFFCR2PFFCR1PFFCR0  PFFEN  
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 16 – PFFRDYDM DMA APB FIFO Data Ready

ValueNameDescription
0CTLINTFLAG_PFFHFULSelects CTLINTFLAG.PFFHFUL for the ADC DMA PFFRDY trigger signal to the DMAC
1CTLINTFLAG_PFFRDYSelects CTLINTFLAG.PFFRDY for the ADC DMA PFFRDY trigger signal to the DMAC

Bit 7 – PFFCR3 APB CORE 3 FIFO Enable

Bit 6 – PFFCR2 APB CORE 2 FIFO Enable

Bit 5 – PFFCR1 APB CORE 1 FIFO Enable

Bit 4 – PFFCR0 APB CORE 0 FIFO Enable

When PFFEN = 1, setting this bit enables the conversion output data of any channel k to be stored into the optional data FIFO.

Note:
  1. This bit is Enabled Protected: (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error).

Bit 1 – PFFEN APB FIFO Enable

When the FIFO is disabled no data is being saved into the FIFO and the its logic is being kept in reset state.

Note:
  1. This bit is Enabled Protected: (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error).
ValueDescription
0FIFO is disabled
1FIFO is enabled