38.7.16 Channel Ready Data Register

Note: All the data read in this register pertains to the Module defined by CORCHDATAID.CORDYID and its analog input channel defined by CORCHDATAID.CHRDYID.

Table 38-23. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CHRDYDAT
Offset:	0x0D4
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
					FRACT	SIGN	DIFF	LVL
Access					R/K	R/K	R/K	R/K
Reset					0	0	0	0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	CHRDYDAT[15:8]
Access	R/K	R/K	R/K	R/K	R/K	R/K	R/K	R/K
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CHRDYDAT[7:0]
Access	R/K	R/K	R/K	R/K	R/K	R/K	R/K	R/K
Reset	0	0	0	0	0	0	0	0

Bit 27 – FRACT Fractional Setting

Bit 26 – SIGN Sign Setting

Bit 25 – DIFF Differential Setting

Bit 24 – LVL Level Setting

Bits 15:0 – CHRDYDAT[15:0] Channel Output Data

Note: A read of CHRDYDAT will generate a read bus error on analog input channels which have not been implemented and the returned data will be 0x0000_0000.