38.7.5 SARCORE Control

Table 38-12. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—


Bit	31	30	29	28	27	26	25	24
		ADCDIV[6:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
		SCNRTDS	STRGLVL		STRGSRC[3:0]
Access		R/W	R/W		R/W	R/W	R/W	R/W
Reset		0	0		0	0	0	0


Bit	15	14	13	12	11	10	9	8
	EIRQOVR	EIS[2:0]			SELRES[1:0]		SAMC[9:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	1	1	0	0


Bit	7	6	5	4	3	2	1	0
	SAMC[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 30:24 – ADCDIV[6:0] Division Ratio for SARCORE clock

ADCDIV provides the ADC analog functional clock referred to as the ADC clock or TAD, (i.e., the period of the ADC clock). It divides CTL_CLK output clock from (GCLK_ADC Period * (CTRLD.CTLCKDIV+1)) with period = TQ to produce the resulting ADC_CLK for ADC sampling and converting. It will have the period TAD given by the formula:

TAD = (GCLK_ADC Period * (CTRLD.CTLCKDIV+1)) * (2 * ADCDIV)

Note: The ADC throughput rate F_TPR = [1 / ((SAMC+2) * TAD) + ((#bits of resolution selected+1)*TAD)] / # of active AINx inputs.

Example 1:

TAD = 1/ADC_CLK = 1/75 MHz = 13.33 ns, SAMC = 0x1, SELRES = 0x3 = 12 bits, AIN0 used only ADC throughput rate

F_TPR = [1 / (3TAD + 13TAD)] / 1

= 1 / 16TAD

= 1 / (16 * 13.33e-9)

= 4.6875 msps

Example 2: (Non Interleaved Mode)

TAD = 1/ADC_CLK = 1/75 MHz = 13.33 ns, SAMC = 0x1, SELRES = 0x3 = 12 bits, AIN0 and AIN3 in single ended mode used ADC throughput rate

F_TPR = [1 / (3TAD + 13TAD)] / 2

= (1 / 16TAD) / 2

= (1 / (16 * 13.33e-9)) / 2

= 4.6875e+6

= 2.34375 msps

Note:

This bit is Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1) . Returns a bus error.
The minimum sample rate for ADC0 is Ftpr >= 100 ksps.
For optimal performance and accuracy, the user must select the maximum TAD clock supported by the device as specified in the ADC electrical specs:
TAD = (GCLK_ADCx Period * (CTRLD.CTLCKDIV+1)) * (2 * ADCDIV)
If the user wishes to control the ADC throughput rate, they must do so by modulating either CORCTRLn.SAMC or the EVSYS trigger interval or both. Do not try to do so by reducing the TAD clock frequency as this will increase the ADC conversion time allowing the charge on the ADC holding capacitor from the sampled analog input signal to leak off, attenuating the ADC result accuracy.

Value	Description
1111111	254·T_Q = T_AD
...	...
0000011	6·T_Q = T_AD
0000010	4·T_Q = T_AD
0000001	2·T_Q = T_AD
0000000	Reserved

Bit 22 – SCNRTDS SCAN Re-trigger Disable

Note:

This bit is Enabled Protected: (Writes are ignored when CTRLA.ENABLE = 1). Returns a bus error.

Value	Description
0	Allows the scan cycle to restart from the beginning, lowest CSSn channel even before all of the scan channels have been measured if a new scan trigger arrives before then. If this happens then the INTENCLR.EOSRDY flag will be set when the current scan is interrupted, and the new scan starts from the beginning of the lowest CSSn channel selected.
1	Prevents an early scan trigger (arriving before of the end of the current scan) from starting a new scan cycle. The scan will include all channels which have their CHNCFG4.TRGSRCk set to point to the Scan Trigger, i.e., CHNCFG4.TRGSRCy[3:0] = 4’b0011, and have their associated CHNCFG2.CSSk bit set.

Bit 21 – STRGLVL Scan Trigger Level Sensitivity

Note:

This bit is Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1). Returns a bus error.

STRGLVL functions as follows:

Value	Description
0	SCANTRG is Positive Edge Active(the power-up value for backwards compatibility). A positive edge on the SCANTRG will initiate a single but complete scan of all included channels.
1	SCANTRG is High Level Active. So long as SCANTRG stays high, the entire scan will re-trigger.

Bits 19:16 – STRGSRC[3:0] SCAN trigger source selection

These bits select the trigger source for the scan trigger SCANTRG. The trigger STRIG serves all the channels k, which have their CHNCFG{4|5}.TRGSRCk = 4’h0011, and have their Channel Scan Select bit set (CHNCFG2.CSSk = 1’b1).

Note:

This bit is Enabled Protected: Writes are ignored when CTRLA.ENABLE = 1 returns a bus error.
In order to utilize CORCTRLn.STRGSRC=0x4, user must configure the following registers:
1. CTRLC.CNT.
2. CHNCFG2n.CSSx.
3. CHNCFG4/5n.TRGSRCx=0x3.
4. CTRLB.SWCNVEN = 0.

Value	Name	Description
0	NO_TRIGGER	No Trigger (NOP)
1	GLOBAL_SOFTWARE_TRIGGER	Global Software Trigger
2	GLOBAL_LEVEL_TRIGGER	Global Level Software Trigger
4	SYNC_TRIGGER	Synchronous Trigger (STRIG)
5	EVENT_USER0	ADC Trigger Event User 0
6	EVENT_USER1	ADC Trigger Event User 1
7	EVENT_USER2	ADC Trigger Event User 2
8	EVENT_USER3	ADC Trigger Event User 3
9	EVENT_USER4	ADC Trigger Event User 4
10	EVENT_USER5	ADC Trigger Event User 5
11	EVENT_USER6	ADC Trigger Event User 6
12	EVENT_USER7	ADC Trigger Event User 7
13	EVENT_USER8	ADC Trigger Event User 8
14	EVENT_USER9	ADC Trigger Event User 9
15	EVENT_USER10	ADC Trigger Event User 10

Bit 15 – EIRQOVR Interrupt Type Select

Note:

This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) . returns a bus error.

Value	Description
0	Use normal ADC interrupts
1	Use early ADC interrupts as defined by CORCTRL.EIS bits

Bits 14:12 – EIS[2:0] Early Interrupt Select

These bits select the number of core clocks and TAD clocks prior to the end of conversion at which the early interrupt is generated. All channels share the same EIS setting.

The interrupt is generated ((EIS +1) x TAD) ADC Module clocks prior to end of conversion.

Note:

This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) . returns a bus error.
Early interrupt is a feature that can be useful in ADC very high speed data acquisitions to mask the MCU interrupt latency delay.
Example: CPU MCLK =72 Mhz, ADC CTL_CLK = 36 MHz and ADC TAD Clk = 18 MHz.
Hypothetically, if it took the CPU 20 MCLK cycles to service an interrupt, then theoretically the ADC early interrupt EIS could be set to 4, hence the ISR latency was masked. The CPU could then read the ADC result almost immediately from within the Interrupt Service Routine (ISR), when the result was ready without any concern for overwriting the current result or FIFO with the next ADC conversion result.

Note: Depending on the bit resolution selection field SELRES, the allowed maximum EIS values are: as follows

12-bit Resolution, all 8 possible settings are allowed, 0 - 7
10-bit Resolution, all 8 possible settings are allowed, 0 - 7
8-bit Resolution, only the 6 lowest settings are allowed, 0 - 5
6-bit Resolution, only the 4 lowest settings are allowed, 0 - 3

The hardware will utilize the maximum allowed EIS setting if the user sets the EIS value that is too big.

CAUTION: Do not set the EIS to large or the interrupt can occur before the ADC conversion is complete and the CPU could read the previous ADC conversion result instead of the one in progress.

Value	Description
0x0	Generate interrupt 1 TAD clock before end of ADC conversion
0x1	Generate interrupt 2 TAD clocks before end of ADC conversion
0x2	Generate interrupt 3 TAD clocks before end of ADC conversion
0x3	Generate interrupt 4 TAD clocks before end of ADC conversion
0x4	Generate interrupt 5 TAD clocks before end of ADC conversion
0x5	Generate interrupt 6 TAD clocks before end of ADC conversion
0x6	Generate interrupt 7 TAD clocks before end of ADC conversion
0x7	Generate interrupt 8 TAD clocks before end of ADC conversion

Bits 11:10 – SELRES[1:0] Selects Resolution

Note:

This bit is Enabled Protected: (Writes are ignored when CTRLA.ENABLE = 1). Returns a bus error.

Value	Name	Description
0	6_BITS	6 bits
1	8_BITS	8 bits
2	10_BITS	10 bits
3	12_BITS	12 bits (power-on default)

Bits 9:0 – SAMC[9:0] Sample Count

The sample time required depends on the external analog signal source impedance. (See ADC electrical characteristics of SAMC values required based on external source impedance. If the external analog source impedance is unknown or if your getting inconsistent ADC results consider increasing the SAMC sample time at the cost of a lower ADC throughput rate of course.

ADC Throughput Rate

F_TPR = [1 / ((SAMC value +2) * TAD) + ((#bits of resolution selected+1)*TAD)] / # of active AINx inputs

Note:

All channels share the same SAMC setting.
The sampling sequence starts with a trigger event.
The internal sampling cap is not discharged between samples.
These bits are Enabled Protected: Writes are ignored when CTRLA.ENABLE = 1 returns a bus error.
When IVREF is to be sampled (SAMC value + 2) * TAD must be ≧ 30 us.

Value	Description
1111111111	1025 T_ADn
...	...
0000000001	3 T_ADn
0000000000	Reserved

Name:	CORCTRL
Offset:	0x020
Reset:	0x00000C00
Property:	RW