38.7.11 SARCORE Calibration Value

Table 38-18. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CALCTRL
Offset:	0x038
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	CALBITS[31:24]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	CALBITS[23:16]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CALBITS[15:8]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CALBITS[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – CALBITS[31:0] Calibration Values

These register bits can only change when the applicable CTRLD.ANLEN0 bit is 0. Once the applicable CTRLD.ANLENn bit rising edge occurs, those bit values must remain unchanged until after the same CTRLD.ANLEN0 bit falling edge occurs.

This register must be initialized in user software to the factory-provided values in the Calibration Configuration Register FCCFG65 before setting CTRLD.ANLENn to 1.

Note:

This bit is Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error).