4.3.1.10 Static Phase Shifting
(Ask a Question)The VCO/4 clock is available in eight phases with a phase difference of 45°. Each PLL clock output can select one of the eight VCO/4 clock phases, independently. This is called VCO phase select. In addition, each PLL clock output can be delayed further up to seven VCO/4 clock cycles, independently. This is accomplished by holding the output divider in reset for the number of specified VCO/4 clock cycles after a reset. This is called VCO reset delay. These two methods can be selected simultaneously for changing the phase of the clock output.
In the example shown in the following figure, Clock_0, Clock_1, Clock_2, and Clock_3 are PLL clock outputs. Clock_1, Clock_2, and Clock_3 are divided clocks of the VCO/4 clock. Clock_0 is the same as the VCO/4 clock. Clock_2 is delayed by one VCO/4 clock cycle and shows the eight possible VCO/4 phases to further delay Clock_2. Clock_3 is delayed by two VCO/4 clock cycles and shows the eight possible VCO/4 phases to further delay Clock_3. All phase delays shown in the following figure are PVT compensated by the PLL.
Phase shifts other than 45° are possible using output dividers. Each output divider is independently programmable, allowing each clock output to have a different phase shift based on the VCO frequency.
The phase shift for PLL clock outputs with respect to the reference clock is configurable using the CCC configurator. The CCC configurator configures the VCO frequency, VCO/4 phase and reset delay, and output dividers based on the requested frequency and phase. If the configurator is not able to generate an exact match of the requested phase shift with respect to the reference clock, it gives two possible phases to select from—one above (actual higher) the requested phase and one below (actual lower) the requested phase.
Phase adjustment can further be made by placing a PLL delay line or DLL delay line in the reference (to push the phase out) or feedback (to pull the phase in) paths of the PLL. It is also possible to place the DLL delay line on the output clocks, but the jitter injected by the DLL delay line is not filtered by the PLL.