4.3.1.3 Clock Outputs

Each PLL has four clock outputs (OUT<3:0>) that can drive global and high-speed I/O clock networks. The CCC_NE clock outputs can drive reference clock inputs of the adjacent transceiver block. The PLL clock output frequency ranges from 1 MHz to 1250 MHz. The OUTDIV2 and OUTDIV3 dividers can be cascaded to generate a slow clock on the OUT3 clock output. For PolarFire SoC and RT PolarFire SoC FPGAs, CCC_NW can generate a reference clock to MSS either from OUT2 or OUT3 clock outputs.

The clock outputs—OUT1 and OUT0 of each PLL can also be connected to preferred clock output pins through low-latency hardwired routing. These preferred clock output pins can be used to drive high-performance clocks in DDR3 and DDR4 applications. The PLL clock outputs are valid only when LOCK is asserted.

During device power-up and programming, the PLLs are powered down and the outputs are driven LOW. The PLL outputs are driven low in the absence of a reference clock. The VDDPLL supply for the PLLs must reach VDD minimum before the power-down of the PLLs is released. For more information about device power-up, see PolarFire Family Device Power-Up and Resets User Guide.

CCC_xy_PLLz_OUTw represents a preferred clock output of one of the PLLs present in a CCC, where:

• xy—represents the CCC location: NE, SE, SW, or NW
• z—represents the PLL identifier: 0 or 1
• w—represents the PLL clock output identifier: 0 or 1