4.3.1.4 Lock Output

(Ask a Question)

The lock signal, PLL_LOCK, indicates that the PLL clock output is locked onto the reference clock. The lock signal is asserted HIGH to indicate that both frequency and phase lock are achieved.

Lock signal assertion and de-assertion depend on the quality of the reference clock signal (including its noise and jitter characteristics), presence or absence of the reference or feedback clock, and excessive noise in the PLL supply. For information about the maximum jitter tolerance, see the respective PolarFire FPGA Datasheet , RT PolarFire FPGA Datasheet , PolarFire SoC FPGA Datasheet , or RT PolarFire SoC FPGA Datasheet .

If the reference clock input of the PLL is disconnected, the user cannot see the PLL output, that is, the output is low with the lock signal becoming 0.

The Lock Delay feature of the PLL is used to avoid false toggling of the lock signal. The lock delay setting indicates the number of post-divided reference clock cycles to wait after the PLL lock is achieved, before asserting the lock signal. The lock delay is fixed and set to 256 PFD cycles.