4.3.1.11 Dynamic Phase Shifting

The dynamic phase shifting feature affects the phase of the PLL clock outputs without reconfiguring the device. All four PLL output clocks have the dynamic phase shifting feature. Each PLL has the following fabric ports for dynamic phase shifting.

The initial phase shift is static phase shift information set through the CCC configurator. The initial phase shift information is loaded into the PLL whenever the PLL is reset (PLL_POWERDOWN_N = 0) or pulsing the LOAD_PHASE_N signal from high-to-low.

User logic is required to vary the VCO phase settings from the initial value. This is achieved by setting the following signals:

1. Phase rotation direction: Set the PHASE_DIRECTION signal, this signal is shared for all four outputs of the same PLL.
2. Determine which PLL outputs have their phase modified: Select the PLL output clock(s) to have its phase modified via the bus PHASE_OUT<0:3>_SEL.

When the preceding setup signals are set, a rising edge on the PHASE_ROTATE signal (shared for all four outputs of each PLL) causes the phase adjustment to take place where the selected PLL outputs can either be rotated forward or backward by one of 8 VCO/4 phases.

It is required that any outputs that have their phase modified through either method must use the clock stop capability (see Clock Start/Stop Input) before phase modification. After performing the required phase shift configuration, the clocks must be started again. The Clock Start/Stop input is not available in post-divider and external feedback modes, use the Global Clock (Gated) option for the CCC outputs other than feedback clock. Each global buffer has a gating option for glitch-free enabling and disabling of the clock. For more information, see Clock Gating.