19.1.10 PMP Status Register (Client Modes Only)
| Name: | PMSTAT |
| Offset: | 0x1C0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| IBF | IBOV | IB[3:0]F | |||||||
| Access | R | R/W | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OBE | OBUF | OB[3:0]E | |||||||
| Access | R | R/W | R | R | R | R | |||
| Reset | 1 | 0 | 1 | 1 | 1 | 1 | |||
Bit 15 – IBF Input Buffer Full Status bit
| Value | Description |
|---|---|
1 |
All writable Input Buffer registers are full |
0 |
Some or all of the writable Input Buffer registers are empty |
Bit 14 – IBOV Input Buffer Overflow Status bit
This bit is set (= 1) in hardware; it can only be
cleared (= 0) in software.
| Value | Description |
|---|---|
1 |
A write attempt to a full input byte buffer occurred (must be cleared in software) |
0 |
No overflow occurred |
Bits 11:8 – IB[3:0]F Input Buffer x Status Full bits
| Value | Description |
|---|---|
1 |
Input buffer contains data that have not been read (reading buffer will clear this bit) |
0 |
Input buffer does not contain any unread data |
Bit 7 – OBE Output Buffer Empty Status bit
| Value | Description |
|---|---|
1 |
All readable Output Buffer registers are empty |
0 |
Some or all of the readable Output Buffer registers are full |
Bit 6 – OBUF Output Buffer Underflow Status bit
This bit is set (= 1) in hardware; it can only be
cleared (= 0) in software.
| Value | Description |
|---|---|
1 |
A read occurred from an empty output byte buffer (must be cleared in software) |
0 |
No underflow occurred |
Bits 3:0 – OB[3:0]E Output Buffer x Status Empty bits
| Value | Description |
|---|---|
1 |
Output buffer is empty (writing data to the buffer will clear this bit) |
0 |
Output buffer contains data that have not been transmitted |