19.1.3 PMP Mode Register

Note:
  1. When WAITM[3:0] = 0000, the WAITBx and WAITEx bits are ignored and forced to 1 TP (peripheral clock) cycle for a write operation; WAITBx = 1 TP cycle, WAITEx = 0 TP cycles for a read operation.
  2. Address bits, A15 and A14, are not subject to auto-increment/decrement if configured as Chip Selects, CS2 and CS1.
  3. These pins are active when MODE16 = 1 (16-bit mode).
  4. The PMADDR register is always incremented/decremented by one, regardless of the transfer data width.

Legend: HC = Hardware Clearable bit; HS = Hardware Settable bit

Name: PMMODE
Offset: 0x1AC

Bit 15141312111098 
 BUSYIRQM[1:0]INCM[1:0]MODE16MODE[1:0] 
Access R/HS/HCR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 WAITB[1:0]WAITM[3:0]WAITE[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 15 – BUSY Busy bit (Host mode only)

ValueDescription
1 Port is busy
0 Port is not busy

Bits 14:13 – IRQM[1:0] Interrupt Request Mode bits

ValueDescription
11

Reserved, do not use
10

Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode), or on a read or write operation when PMA[1:0] = 11 (Addressable Client mode only)
01

Interrupt generated at the end of the read/write cycle
00

No interrupt generated

Bits 12:11 – INCM[1:0] Increment Mode bits

ValueDescription
11

Client mode read and write buffers auto-increment (MODE[1:0] (PMMODE[9:8]) = 00 only)
10

Decrements ADDR[15:0] by one every read/write cycle(2,4)
01

Increments ADDR[15:0] by one every read/write cycle(2,4)
00

No increment or decrement of address

Bit 10 – MODE16 8/16-Bit Mode bit

ValueDescription
1

16-Bit Mode: A read or write to the Data register invokes a single 16-bit transfer
0

8-Bit Mode: A read or write to the Data register invokes a single 8-bit transfer

Bits 9:8 – MODE[1:0] PMP Mode Select bits

ValueDescription
11

Host Mode 1 (PMCSx, PMRD, PMWR, PMENB, PMA[x:0], PMD[7:0], PMD[8:15])(3)
10

Host Mode 2 (PMCSx, PMRD, PMWR, PMA[x:0], PMD[7:0] and PMD[8:15])(3)
01 Enhanced Client mode, controls signals (PMRD, PMWR, PMCS, PMD[7:0] and PMA[1:0])
00

Legacy Parallel Client Port mode, controls signals (PMRD, PMWR, PMCS and PMD[7:0])

Bits 7:6 – WAITB[1:0]  Data Setup to Read/Write Strobe Wait States bits(1)

ValueDescription
11

Data Wait of 4 TP; multiplexed address phase of 4 TP
10

Data Wait of 3 TP; multiplexed address phase of 3 TP
01

Data Wait of 2 TP; multiplexed address phase of 2 TP
00

Data Wait of 1 TP; multiplexed address phase of 1 TP (default)

Bits 5:2 – WAITM[3:0]  Data Read/Write Strobe Wait States bits(1)

ValueDescription
1111

Wait of 16 TP
. . .
0001

Wait of 2 TP
0000

Wait of 1 TP (default)

Bits 1:0 – WAITE[1:0]  Data Hold After Read/Write Strobe Wait States bits(1)

11 = Wait of 4 TP

10 = Wait of 3 TP

01 = Wait of 2 TP

00 = Wait of 1 TP (default)

For Read Operations:

11 = Wait of 3 TP

10 = Wait of 2 TP

01 = Wait of 1 TP

00 = Wait of 0 TP (default)