19.1.9 PMP Pin Enable Register

Note:

The use of these pins as address or Chip Select lines is selected by the CSF[1:0] bits (PMCON[7:6]).
The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode selected by the ADRMUX[1:0] bits in the PMCON register.

Name:	PMAEN
Offset:	0x1BC


Bit	15	14	13	12	11	10	9	8
	PTEN[15:14]		PTEN[13:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PTEN[7:2]						PTEN[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:14 – PTEN[15:14] PMCSx Strobe Enable bits

Value	Description
`1`	PMA15 and PMA14 function as either PMA[15:14] or PMCS2 and PMCS1⁽¹⁾
`0`	PMA15 and PMA14 function as port I/Os

Bits 13:2 – PTEN[13:2] PMP Address Port Enable bits

Value	Description
`1`	PMA[13:2] function as PMP address lines
`0`	PMA[13:2] function as port I/Os

Bits 1:0 – PTEN[1:0] PMALH/PMALL Strobe Enable bits

Value	Description
`1`	PMA1 and PMA0 function as either PMA[1:0] or PMALH and PMALL⁽²⁾
`0`	PMA1 and PMA0 pads function as port I/Os

DS70005452D

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