19.1.2 PMP Control High Register

Note:
  1. This bit is cleared by HW at the end of the read cycle when BUSY (PMMODE[15]) = 0.

Legend: HC = Hardware Clearable bit

Name: PMCONH
Offset: 0x1AA

Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 RDSTART     DUALBUF  
Access R/W/HCR/W 
Reset 00 

Bit 7 – RDSTART  Start a Read on PMP Bus bit(1)

ValueDescription
1 Starts a read cycle on the PMP bus
0 No effect

Bit 1 – DUALBUF PMP Dual Read/Write Buffers Enable bit (valid in Host mode only)

ValueDescription
1 PMP uses separate registers for reads and writes (PMRADDR, PMDINx, PMWADDR, PMDOUTx)
0 PMP uses legacy registers (PMADDR, PMDINx)