31.19 Digital-to-Analog Controller (DAC) Specifications
| AC CHARACTERISTICS | Standard Operating Conditions: VDDIO = AVDD = VDD 1.62V to
3.63V (unless otherwise stated) Operating Temperature:: -40°C ≤ TA ≤ +85°C for Industrial | |||||||
|---|---|---|---|---|---|---|---|---|
| Param. No. | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions | |
| DAC_1 | DRES | DAC Resolution | — | — | 10 | Bits | — | |
| DAC_3 | DCLK | Internal DAC Clock Frequency (GCLK_DAC) | — | — | FCLK_53 | MHz | — | |
| DAC_5 | DSAMP | DAC Sampling Rate | — | — | 350 | Ksps | +/-4 LSB of final value for step size ≤ 100 LSb at CLOAD and RLOAD | |
| DAC_7 | VOUT | Output Voltage Linear Range | AGND+0.1V | — | AVDD-0.1V | V | External Pin (Buffered) VREF = AVDD at CLOAD and RLOAD | |
| AGND+0.1V | — | VREF | V | External Pin (Buffered) at CLOAD and RLOAD (VREF < (AVDD-100 mV)) | ||||
| AGND | — | VREF | V | Internal connection to another module (for example, AC) (No buffer) | ||||
| DAC_9 | VREF(1) | DAC Reference Input Option | INT1V CTRLB.REFSEL = 0x0 | Specification VR_1 to VR_3 | V | Internal Reference | ||
| AVDD CTRLB.REFSEL = 0x1 | 2.4 | — | AVDD | V | VREF = AVDD | |||
| VREFA pin CTRLB.REFSEL = 0x2 | 2.4 | — | AVDD - 0.6V | V | External Reference
VREFA (buffered) VREF bypass Cap = 4.7 µF // 100 nF | |||
| DAC_11 | CLOAD | DAC Out maximum load to meet VOUT and TSET | — | — | 100 | pF | — | |
| DAC_13 | RLOAD | DAC Out maximum load to meet VOUT and TSET | 5 | — | — | KΩ | — | |
| DAC_15 | Tset | DAC Settling Time | — | — | 1 | µs | +/-4 LSB of final value for step size ≤ 4 LSb at CLOAD and RLOAD w/ AVDD = 3.3V | |
| DAC_17 | Tset_FS | DAC Full Scale Settling Time | — | — | 2.85 | µs | +/-4 LSB of final value for step size from 10% to 90% at CLOAD and RLOAD w/ AVDD = 3.3V | |
| SINGLE ENDED MODE(1,2,3) | ||||||||
| SDAC_19 | INL(3) | Integral Non Linearity | -2.0 | — | 2.0 | LSB | CTRLB.REFSEL = 0x1
VREF = AVDD = 3.3V w/ CLOAD and RLOAD | |
| -1.3 | — | 1.3 | LSB | CTRLB.REFSEL = 0x2
AVDD = 3.3V VREF = VREFA w/ CLOAD and RLOAD | ||||
| SDAC_21 | DNL(3) | Differential Non Linearity | -0.5 | — | 0.5 | LSB | CTRLB.REFSEL = 0x1
VREF = AVDD = 3.3V w/ CLOAD and RLOAD | |
| -0.7 | — | 0.7 | LSB | CTRLB.REFSEL = 0x2
AVDD = 3.3V VREF = VREFA w/ CLOAD and RLOAD | ||||
| SDAC_23 | GERR(3) | Gain Error | -13.8 | — | -4.6 | LSB | CTRLB.REFSEL = 0x1 VREF = AVDD = 3.3V w/ CLOAD and RLOAD | |
| -5.0 | — | -0.2 | LSB | CTRLB.REFSEL = 0x2
AVDD = 3.3V VREF = VREFA w/ CLOAD and RLOAD | ||||
| SDAC_25 | EOFF(3) | Offset Error | -3.1 | — | 3.1 | LSB | CTRLB.REFSEL = 0x1
VREF = AVDD = 3.3V w/ CLOAD and RLOAD | |
| -4.5 | — | 4.5 | LSB | CTRLB.REFSEL = 0x2
AVDD = 3.3V VREF = VREFA w/ CLOAD and RLOAD | ||||
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Note:
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