31.18 DFLL48M Electrical Specifications

Table 31-20. Digital Frequency Locked Loop (DFLL48M) Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDDIO = AVDD = VDD 1.62V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
DFLL48MHz (Closed Loop)^(1,2,3)
DFLL_11	DFLL_CL_FI⁽²⁾	DFLL Closed- Loop Input Frequency Range	0.732	32.768	35.1	KHz	—
DFLL_13	DFLL_CL_FOUT	DFLL Closed- Loop Clock Frequency	47	48	49	MHz	XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 1464 DFLLVAL.FINE = 512
DFLL_15	DFLL_CL_Jitter	DFLL Period Jitter Pk-to-Pk	—	—	5.0	%	VDDIO = 3.3V, Closed- Loop mode, XOSC32 32.768 kHz PPM ≤ 100 DFLLMUL = 1464 DFLLVAL.FINE = 512
DFLL_21	DFLL_CL_SRT⁽³⁾	DFLL Closed- Loop Mode/Lock Time	—	—	1.5	ms	VDDIO = 3.3V, Closed-Loop mode, XOSC32 32.768 kHz PPM ≤ 100
Note: In Closed-Loop mode the DFLL can use a variety of clock sources. The DFLL can be trimmed using the DFLLMUL register. To ensure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in close loop must be within a 2% error accuracy. DFLLMUL = 1464, DFLLVAL.FINE = 512, DFLLCTRL.BPLCKC = 1: only fine value change, coarse value locked to the reset value. DFLLCTRL.QLDIS = 0: quick lock enable, DFLLCTRL.CCDIS = 1: Enabling chill cycles might double the lock time. DFLLMUL.FSTEP = 10: maximum fine step size, divided or dividing into two parts, search. 10 is a optimum value.