31.3 Power Supply

Table 31-5. Power Supply DC Electrical Specifications
DC CHARACTERISTICS			Standard Operating Conditions: VDDIO = AVDD = VDD 1.62V to 3.63V (unless otherwise stated) Operating Temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
REG_1	VDDCORE_CIN⁽¹⁾	VDDCORE Input Bypass parallel Capacitor pair	0.8	1	1.2	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω. Minimum and maximum represent absolute values including cap tolerances.
REG_3	VDDCORE_CIN⁽¹⁾	VDDCORE Input Bypass parallel Capacitor pair	80	100	—	nF	Ceramic X7R with ESR <0.5Ω
REG_4	VDDIO_CIN⁽¹⁾	VDDIO Input Bypass parallel Capacitor pair	8	10⁽⁶⁾	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω⁽²⁾
REG_5	VDDIO_CIN⁽¹⁾	VDDIO Input Bypass parallel Capacitor pair	80	100	—	nF	Ceramic X7R with ESR <0.5Ω on all VDDIO pins
REG_6	VDDIN_CIN⁽¹⁾	VDDIN Input Bypass parallel Capacitor pair	8	10	—	nF	Ceramic X7R with ESR <0.5Ω
REG_7a			0.8	1	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω⁽²⁾
REG_7b			8	10⁽⁷⁾	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω⁽²⁾
REG_8			80	100	—	nF	Ceramic X7R with ESR <0.5Ω on all VDDIO pins
REG_9	VREFA/B_CIN⁽¹⁾	External VREFA/B Input Bypass parallel Capacitor pair	3.76	4.7	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_9	VREFA/B_CIN⁽¹⁾	External VREFA/B Input Bypass parallel Capacitor pair	80	100	—	nF	Ceramic X7R with ESR <0.5Ω
REG_17	AVDD_CIN⁽¹⁾	AVDD Input Bypass parallel Capacitor pair	8	10	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω⁽²⁾
REG_19	AVDD_CIN⁽¹⁾	AVDD Input Bypass parallel Capacitor pair	80	100	—	nF	Ceramic X7R with ESR <0.5Ω
REG_23	AVDD_LEXT	AVDD series Ferrite Bead DCR (DC Resistance)	—	—	0.1	Ω	≥600 Ω @ 100 MHz
REG_25	AVDD_LEXT	Ferrite Bead current Rating	500	—	—	mA	—
REG_36	VDDCORE	DC calibrated output voltage	1.1	1.23	1.30	V	—
REG_37	VDDIO, VDDIN, AVDD⁽³⁾	VDDIO, VDDIN, AVDD Input Voltage Range	1.62	—	3.63	V	—
REG_43	SVDDIO/VDD_R	VDDIN, AVDD, VDDIO Rise Ramp Rate to Ensure Internal Power-on Reset Signal	0.004	—	0.1	V/µs	Failure to meet this specification may lead to startup failure or unexpected behaviors. Note: The Minimum Supply Rise Rate does not apply if the voltage on the Reset pin is lower than the VILmax value, until VDD reaches 1.62 V.
REG_44	SVDDIO/VDD_F	VDDIN, AVDD, VDDIO Fall Ramp Rate to Ensure Internal Power-on Reset Signal	—	—	0.05	V/µs	Failure to meet this specification may cause the device to not detect reset
REG_45a	VPOR+	VDDIO/VDD Rising Power-on Reset	1.27	1.45	1.58	V	VDDIO/VDD power-up/power-down (See Param REG43, VDDIO/VDD Rise Ramp Rate )
REG_45b	VPOR-	VDDIO/VDD Falling Power-on Reset	0.72	0.99	1.32	V	VDDIO/VDD Power-up/Power-down (See Param REG43, VDDIO/VDD Fall Ramp Rate )
REG_47	VBOD33^(4,5)	VDD BOD (All modes)^(4,5)	1.61	—	1.67	V	(Default Setting) LEVEL[ 5:0] = 0x6 ⁽⁴⁾ HYST[0] = 0x0
			1.61	—	1.75	V	(Default Setting) LEVEL[5:0] = 0x6 ^(4,5) HYST[0] = 0x1
			1.64	—	1.71	V	(Default Setting) LEVEL[ 5:0] = 0x7 ⁽⁴⁾ HYST[0] = 0x0
			1.64	—	1.79	V	(Default Setting) LEVEL[5:0] = 0x7 ^(4,5) HYST[0] = 0x1
			2.55	—	2.65	V	(Default Setting) LEVEL[ 5:0] = 0x22 ⁽⁴⁾ HYST[0] = 0x0
			2.55	—	2.75	V	(Default Setting) LEVEL[5:0] = 0x22^(4,5) HYST[0] = 0x1
			2.72	—	2.81	V	(Default Setting) LEVEL[ 5:0] = 0x27⁽⁴⁾ HYST[0] = 0x0
			2.72	—	2.92	V	(Default Setting) LEVEL[5:0] = 0x27^(4,5) HYST[0] = 0x1
			3.02	—	3.20	V	LEVEL[ 5:0] = 0x30⁽⁴⁾ HYST[0] = 0x0
			3.02	—	3.33	V	LEVEL[ 5:0] = 0x30^(4,5) HYST[0] = 0x1
REG_51	VBOD33LEVEL_STEP	VBOD33 step size, LEVEL[7:0]	—	34	—	mV	Step Size
REG_52	VBOD33HYST_STEP	VBOD33 Hysteresis step size, HYST[3:0]	—	See⁽⁵⁾	—	mV	Step Size
REG_53	TRST	External RESET valid active pulse width	1	—	—	µs	Minimum reset active time to guarantee MCU reset
Note: All bypass caps should be located immediately adjacent to pins and on the same side of the PCB as the MCU. Only one bulk capacitor (REG_4 or REG_7) is enough for both VDDIN and VDDIO. VDDIN and AVDD must be at the same voltage level. VDDIO should be lower or equal to VDDIN/AVDD. The common voltage is referred to as VDD in the data sheet. Some I/O are in the VDDIO cluster, but can be multiplexed as analog inputs or outputs (e.g. PTC.X[n] pads). In such a case, AVDD is used to power the I/O. Using this configuration may result in an electrical conflict if the VDDIO voltage is lower than the VDDIN/AVDD. VBOD33(min) = 1.404 + d(BOD33.LEVEL[5:0]) * 0.034. VBOD33(max) at BOD33.HYST[0] = 1 = VBOD33(max) at BOD33.HYST[0] = 0 + VBOD33HYST_STEP. Shared between VDDIO, VDDIN, and AVDD.