1.5.4.4.4 XCVR REFCLK Usage

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Transceiver Reference clock input standards will default to the following configurations dependent on the selection of LVCMOS, Voltage Reference, or Differential selection in the REFCLK configurator.

Table 1-22. XCVR REFCLK Defaults
Reference Clock Mode	I/O Std	Resistor Pull	Schmitt Trigger	ODT	VDDI
LVCMOS	LVCMOS25	None	OFF	0	2.5
Voltage Reference	SSTL25I	None	OFF	0	2.5
Differential	LVDS25	None	OFF	100	2.5

The default can be changed using I/O PDC constraints (not available in IOEditor).


-io_std <iostd>
-ODT_VALUE <odt>
-RES_PULL <res_pull>
-SCHMITT_TRIGGER <schmitt> 
-USE_EXTERNAL_VREF <true, false> 
-POWER_SUPPLY <power Supply for all Ports> 
-EXTERNAL_VREF <true/false>

Important:

By default, the VDD_XCVR_CLK power supply is set to 2.5V. If 3.3V is used, add all ports in the PDC. If a port is not specified in the PDC, it takes the default settings. All REFCLK ports must be specified in the PDC to specify their location else the flow stops.
The new options are case sensitive, the values are not.
To turn OFF the odt, set the ODT_VALUE to 0.
SSTL18I, SSTL18II, SSTL25I, and SSTL25II inputs optionally have a VREF pin to set.
The PDC option is called USE_EXTERNAL_VREF <true/false> where the default is false to use the internal VREF pin.

Table 1-23. Reference Clock Input Buffer Standards¹
Single-ended	Differential²	Reference Voltage (Not supported for ES/XT devices).
LVCMOS18 (VDDI = 2.5)	HCSL25³	HSUL18I (VDDI = 2.5)
LVCMOS25 (VDDI = 2.5)	LVDS25	HSUL18II (VDDI = 2.5)
LVCMOS33 (VDDI = 3.3)	LVPECL33 (VDDI = 3.3)	SSTL18I (VDDI = 2.5)
LVTTL (VDDI = 3.3)	MINILVDS25	SSTL18II (VDDI = 2.5)
—	MIPI25	SSTL25I (VDDI = 2.5)
—	MLVDS25	SSTL25II (VDDI = 2.5)
—	PPDS25	—
—	RSDS25	—
—	SLVS25	—
—	SUBLVDS25	—
—	LVDS33⁴	—
⁽¹⁾ VDDI = VDD_XCVR_CLK ⁽²⁾ Differential inputs do not include internal voltage-bias circuitry. ⁽³⁾ LP-HCSL is supported with HCSL25 reference clock setting without 100Ω differential ODT. ⁽⁴⁾ LVDS33 is supported in device with VDDI= 3.3 V and supported in Libero by selecting LVDS25 IO Standard configuration.

Users need to be aware of power supply requirements and voltage reference requirements. See PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide for more information.