1.5.4.4.1 Differential Input

This mode supports differential inputs such as LVDS/HCSL. The differential reference clock is available on REFCLK0 (REFCLK1 is not available with differential input clock mode). The inputs include an optional on-die 100Ω differential termination resistor. By default, the differential input termination resistance is set in high-Z mode until programmed with Libero software. XCVR_VREF is not used for differential reference clock input signaling. XCVR_VREF is used for single-ended signals requiring a voltage reference, such as SSTL.