24.5.28 Pattern Generation Mode Output Buffer

Name:	PGMOUTBUF
Offset:	0x1D
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
	PGMOUTBUF7	PGMOUTBUF6	PGMOUTBUF5	PGMOUTBUF4	PGMOUTBUF3	PGMOUTBUF2	PGMOUTBUF1	PGMOUTBUF0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – PGMOUTBUF Pattern Generation Mode Output Buffer

This register is the buffer for the Pattern Generation Mode Output (WEXn.PGMOUT) register. If using double-buffering, the valid content in this register is copied to the WEXn.PGMOUT register on an UPDATE condition.

This register is used only when enabling Pattern Generation mode (PGM = ‘1’ in the Control A (WEXn.CTRLA) register).

The table below shows the available configuration for each bit n in this bit field:

Value	Description
0	Waveform output value for Pin n (Pxn) is driven low
1	Waveform output value for Pin n (Pxn) is driven high