24.5.10 Fault Control
| Name: | FAULTCTRL |
| Offset: | 0x0A |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FDDBD | FDMODE | FDACT[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 7 – FDDBD Fault Detection on Debug Break Detection
| Value | Name | Description |
|---|---|---|
| 0x0 | FAULT | On Chip Debug Break request is treated as a fault if fault protection is enabled |
| 0x1 | IGNORE | On Chip Debug Break request will not trigger a fault |
Bit 2 – FDMODE Fault Detection Restart Mode
| Value | Name | Description |
|---|---|---|
| 0x0 | LATCHED | Latched mode. The output will remain in a Fault state until the Fault condition is no longer active and Fault Detection Flag Event Input (FDFEVx in INTCTRL register) is cleared by software. |
| 0x1 | CBC | Cycle-by-Cycle mode. Waveform output will remain in a Fault state until the Fault condition is no longer active. |
Bits 1:0 – FDACT[1:0] Fault Detection Action
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | None. Fault protection disabled. |
| 0x1 | LOW | Drive all pins low |
| 0x2 | - | Reserved |
| 0x3 | CUSTOM | Drive all pins to the settings defined by the Fault Drive (WEXn.FAULTDRV) and Fault Output (WEXn.FAULTOUT) registers |