This register is used for
both the value to be written in the cache RAM location and the compare value
for a location.
There are a total of four
CHEDAT registers for inspection of the entire cache data word N. See Register Summary for the
full SFR map.
User software should not
attempt to write to this register on the instruction cycle immediately
following a read via the CHECMD SFR. If this is done, the write contents
will be lost due to the hardware read of this register.
Name:
CHEDAT
Offset:
0x1E6C,0x1E70,0x1E74,0x1E78
Bit
31
30
29
28
27
26
25
24
WORD[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
WORD[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
WORD[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
WORD[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:24 – WORD[31:24] MSB of 32-bit
Instruction Word N in Cache Line bits
Bits 23:16 – WORD[23:16] Third byte of
32-bit Instruction Word N in Cache Line bits
Bits 15:8 – WORD[15:8] Second Byte of 32
bit Instruction Word N in Cache Line bits
Bits 7:0 – WORD[7:0] LSB of 32-bit
Instruction Word N in Cache Line bits
DS70005629B
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
