3.4.2.2 Cache Status Register
| Name: | CHESTAT |
| Offset: | 0x1E64 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ISBPE | TPE | ISBE | PARE | ||||||
| Access | R/C/HS | R/C/HS | R/W | R/S/HC | |||||
| Reset | 0 | 0 | 1 | 1 |
Bit 3 – ISBPE ISB Parity Error Status bit
| Value | Description |
|---|---|
| 1 | An ISB FIFO read parity error event has occurred. The CPU has fetched a word from the ISB with a parity error, resulting in a PBU miss event, or a diagnostic read initiated by the ISBCMD register has resulted in a parity error. |
| 0 | No ISB FIFO read error event has occurred. |
Bit 2 – TPE TAG Parity Error Status bit
| Value | Description |
|---|---|
| 1 | A TAG memory read parity error event has occurred. The CPU has fetched a word from the cache with a TAG parity error, resulting in a PBU miss event, or a diagnostic read initiated by the TAGCMD register has resulted in a parity error. |
| 0 | No TAG memory read error event has occurred. |
Bit 1 – ISBE Read Error Status bit
| Value | Description |
|---|---|
| 1 | A read error event has occurred; the CPU has fetched a word from the ISB with a security error. |
| 0 | No read error event has occurred. |
Bit 0 – PARE Cache Parity Error Status bit
| Value | Description |
|---|---|
| 1 | A parity error event has occurred; the CPU has fetched a word from the cache with a parity error. |
| 0 | No parity error event has occurred. |