3.4.2.3 Cache Fault Injection Register
Note: There are 132 bit lines which cover the 128 bit data, in
addition to 1 parity bit per 32 bit data entry in the cache line.
| Name: | CHEFLTINJ |
| Offset: | 0x1E68 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTPTR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
Bits 7:0 – FLTPTR[7:0] Fault Injection Pointer bits
| Value | Description |
|---|---|
| 255-129 | No effect |
| 131 | Bit 131 of cache data line |
| 130 | Bit 130 of cache data line |
| ... | |
| 1 | Bit 1 of cache data line |
| 0 | Bit 0 of cache data line |