3.4.2.1 Cache Control Register

Note:
  1. After being set, this bit will be cleared by hardware after the cache and ISB invalidations are completed. Any automatic invalidation will also result in this bit being cleared.
  2. This setting is useful when programming non-program data into Flash (emulated EEPROM).
  3. After the event of software set or software clear of the ON bit, all cache lines and all ISBs are invalidated. This is true if the CP bit is 0 or 1.
  4. Do not perform diagnostics on the ISB that is currently in use by the PBU module. If ISBBUF is 0, do not execute diagnostics on ISBBUF_0.
  5. ON 1≥0 and CP 1≥0 at the same time, clearing the ON has priority.
  6. The CP and ON bits are intended to be used independently. If the ON bit is toggled while paused, a cache invalidation occurs.
Name: CHECON
Offset: 0x1E60

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
        ISBBUF 
Access R/W 
Reset 0 
Bit 15141312111098 
 ON   CHEINVCHECOH   
Access R/WR/S/HCR/W 
Reset 111 
Bit 76543210 
        FLTINJ 
Access R/S/HC 
Reset 1 

Bit 16 – ISBBUF ISB Buffer Selection bit

ValueDescription
1 When ON = 0 or (ON = 1 and CP = 1), ISB buffer 0 will be used for prefetch.
0 When ON = 0 or (ON = 1 and CP = 1), ISB buffer 1 will be used for prefetch.

Bit 15 – ON Cache ON bit

ValueDescription
1 Cache and all ISB slices are enabled.
0 All cache lines and ISB buffers, except for the first buffer slice, are invalidated. ISB operates with one buffer slice, creating a two-deep buffer (basic Prefetch mode).

Bit 11 – CHEINV  Manual Invalidate Control bit(1)

ValueDescription
1 Force invalidation of all cache and ISB lines.
0 Invalidation of the Instruction Cache and ISBs occurs according to the CHECOH bit.

Bit 10 – CHECOH  Cache Coherency Control bit(2)

ValueDescription
1 Invalidate the cache upon a Flash programming event.
0 Do not invalidate the cache on a Flash programming event.

Bit 0 – FLTINJ Fault Inject Control bit

ValueDescription
1 Parity Fault injection enabled for one-time event; cache line will be invalidated and flushed when access occurs, and upbs_event[1] will be asserted to indicate an integrity error to the system.
0 Parity Fault injection disabled.