The CMPP and CMPD control
bits require a minimum of three CPU clocks to complete once set. There must
be at least three CPU clock cycles before reading the result.
CHECON.ISBBUF should be set
to 0 when performing diagnostics via the ISBCMD1_7
register. Otherwise, unexpected results may occur.
CMPD is checked when
comparing the contents of the ISB Buffer to the ISBDAT data register. If
CMPD and RD are both set, RD will be ignored.
WD and WP are active only for
valid slices, in this case, Slice 1 to 3, and for Line 0 & 1.
For ISB DAT REG =
0, 1, 2, or
3, the write and compare operations will ignore the 4
least significant bits of ISBDAT[0].
With all the ISB DAT REG,
users should never attempt to write a value that exceeds the maximum number
of lines in an ISB.
Name:
ISBCMD0
Offset:
0x1E98
Bit
31
30
29
28
27
26
25
24
RIP[3:0]
WIP[3:0]
Access
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
CMPP
EWD
EWP
CMPD
RD
Access
R/W/HS/HC
W
W
R/W/HS/HC
W
Reset
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
LINE[2:0]
Access
R/W
R/W
R/W
Reset
0
0
0
Bit
7
6
5
4
3
2
1
0
ISBREG[2:0]
Access
R/W
R/W
R/W
Reset
0
0
0
Bits 31:28 – RIP[3:0] Valid When Reading
ISB Data Register bits
Compare the contents of parity
bits only if ISBREG is set to 101, which equals
isb_slice_data.
Bit 21 – EWD
Set to 1 when the control
register is written; causes DATA bits to be written manually.
Bit 20 – EWP
Set to 1 when the control
register is written; causes PARITY bits to be written
manually.
Bit 19 – CMPD
Compare the contents of the
addressed ISB register to the contents of data registers.
Bit 18 – RD
Read/write four 32-bit
register values to address cache RAM, parity bits into
ISBCMD.RIP.
Value
Description
1
READ
0
No
action taken.
Bits 10:8 – LINE[2:0] ISB Buffer Line
Address bits, 0-7
Value
Description
111
line #7
...
...
010
line #2
001
line #1
000
line #0
Bits 7:5 – ISBREG[2:0]
Specifies the ISB register
within a slice to be accessed.
Value
Description
111
NOP
110
NOP
101
isb_slice_data
100
fifo_entry_count
011
stream_start_address
010
fifo_head_addr
001
NOP
000
nvm_prefetch_addr
DS70005629B
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
