3.4.2.10 ISB Command 1-7 Control Register
Note:
- The ISBCMD0 register allows for diagnostics of ISB0, while ISB1 is used for buffering. ISB1 is assigned for buffering using the CHECON.ISBBUF control bit.
- Any diagnostic accesses via the ISBCMD1_7 register when ISB1 has been selected for buffering using CHECON.ISBBUF is a user error and may lead to unexpected results.
- The CMPP and CMPD control bits require a minimum of three CPU clocks to complete once set. There must be at least three CPU clock cycles before reading the result.
- WD & WP are only active for valid slices, in this case, Slice 0, and for Line 0 & 1 within the slice.
- For ISB DAT REG =
0,1,2, or3, the write and compare operations will ignore the 4 least significant bits of ISBDAT[0]. - With all the ISB DAT REG, users should never attempt to write a value that exceeds the maximum number of lines in an ISB.
| Name: | ISBCMD1_7 |
| Offset: | 0x1E9C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RIP[3:0] | WIP[3:0] | ||||||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CMPP | EWD | EWP | CMPD | RD | |||||
| Access | R/W/HS/HC | W | W | R/W/HS/HC | W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LINE[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ISBREG[2:0] | SLICE[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 31:28 – RIP[3:0] Valid When Reading ISB Data Register bits
Bits 27:24 – WIP[3:0] Write Parity Data, Requires EWP = 1 bits
Bit 22 – CMPP
Bit 21 – EWD
Bit 20 – EWP Set to 1 when control register is written; causes PARITY bits to be written manually
Bit 19 – CMPD
Bit 18 – RD
| Value | Description |
|---|---|
| 1 | READ |
| 0 | No action taken. |
Bits 10:8 – LINE[2:0] ISB Buffer Line Address bits, 0-7
| Value | Description |
|---|---|
| 111 | line #7 |
| ... | ... |
| 010 | line #2 |
| 001 | line #1 |
| 000 | line #0 |
Bits 7:5 – ISBREG[2:0]
| Value | Description |
|---|---|
| 111 | NOP |
| 110 | NOP |
| 101 | isb_slice_data |
| 100 | fifo_entry_count |
| 011 | stream_start_address |
| 010 | fifo_head_addr |
| 001 | NOP |
| 000 | nvm_prefetch_addr |
Bits 2:0 – SLICE[2:0] ISB buffer slice address, 0-7
| Value | Description |
|---|---|
| 111 | slice #7 |
| ... | ... |
| 010 | slice #2 |
| 001 | slice #1 |
| 000 | slice #0 (NOP) NOT VALID, there is a separate control register for ISB slice 0 |