3.4.2.7 Tag Command Register (Address/Control)

Note:

The CMPP and CMPA control bits require a minimum of three CPU clocks to complete the comparison and get set before reading the result.
The CMPA bit has priority over the RD bit. If the RD bit is set simultaneously with the CMPD bit, then the read operation will be ignored because the data comparison operation has priority.

Name:	TAGCMD
Offset:	0x1E84


Bit	31	30	29	28	27	26	25	24
						RTP0	WTP0
Access						R/HS/HC	R/W
Reset						0	0


Bit	23	22	21	20	19	18	17	16
		CMPP	EWP	EWD	CMPA	RD
Access		R/W/HS/HC	R/W	R/W	R/W/HS/HC	W
Reset		0	0	0	0	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
		ADDR[6:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bit 26 – RTP0 Read Value of TAG Parity bit 0

Bit 25 – WTP0

Direct write of the TAG parity bit 0 (when enabled by bit 20), readback of written data.

Bit 22 – CMPP

Compare the contents of the addressed cache TAG parity to the WIP0 bit in this register. In READ mode, the register will return the result of the comparison.

Value	Description
1	Compare result is good.
0	Compare result has an error.

Bit 21 – EWP

Enable the single bit of parity to be directly written to the parity bits in the TAG RAM.

Bit 20 – EWD

Enable 24-bit address in the data register to be written to TAG RAM.

Bit 19 – CMPA

Compare the contents of the addressed cache TAG entry to the contents of the address register. In READ mode, the register will return the result of the comparison.

Value	Description
1	Compare result is good.
0	Compare result has an error.

Bit 18 – RD

Read/write four 32-bit register values to address cache RAM.

Value	Description
1	Trigger a single READ event.
0	No event.