3.4.4.7 Cache HIT Logic

Each line of the Instruction Cache memory has a Tag address register based on the number of cache lines. The number of bits in the Tag address depends on the number of implemented cache memory lines. The Tag address is derived from the most significant bits of the CPU program fetch address.

Figure 3-25 shows how the Tag and cache line addresses are derived from the PC address for a direct-mapped and set-associative cache, respectively.

Bits 3:0 of the program fetch address are not used to form the Tag or cache line address since the cached data size is 16 bytes (four 32-bit words).