3.4.4.3 Module Operation When Cache Disabled

When the CHECON.ON bit is 0, all cache operations and advanced ISB operations are disabled. The PBU behaves as a single 2-level prefetch buffer. The single prefetch buffer provides one location for the CPU to consume program data. The appropriate 32-bit portion of the 128-bit program word is supplied to the CPU based on address bits 3:2 of the PC address. The other location in the prefetch buffer predictively fetches the next sequential program memory location (PC + 16).

If no program flow changes occur, the 2-level prefetch buffer is able to keep pace with linear program flow without wait states. This assumes that each fetch from program memory takes 4 clock cycles, and each program word contains at least 4 instructions.

Each line of the prefetch buffer is invalidated when the CPU has consumed the last instruction word (highest address) in the line. If a program flow change occurs outside of the current program data word, the prefetch buffer is invalidated, and a new fetch begins at the requested address.

The number of clock cycles required to fetch the new target address will vary depending on which instruction word in the prefetch line caused the flow change. This is because a prefetch that is already in progress from Flash memory will not be aborted. Therefore, the prefetch buffer must wait for the fetch in progress to be completed before the fetch at the new target location can begin.