3.4.4.13 Cache Coherency

Coherency between cached values in the PBU and Flash must be maintained after Flash write events, a panel swap BOOTSWP operation, and in the event of a cache/ISB parity error. This is achieved through automatic instruction cache and ISB invalidation, though it is optional during Flash programming, and only affects the faulted cache line or ISB in the event of a parity error.

The contents of the cache memory and ISBs can be invalidated manually by setting the CHEINV bit. If the application is operating from Flash memory, then a stall will occur until all contents of the PBU are invalidated and the next program data word can be fetched from Flash memory.